17
GLOBAL ENERGY EFFICIENCY SPECIALIST
ADF10S48B
AC-DC Converter Technical Manual V1.1
PMBus Timing
The module supports both 100 kHz (default) and
400 kHz clock rates.
T
set
is the duration for which SDA keeps its value
unchanged before SCL increases. T
hold
is the
duration for which SDA keeps its value unchanged
after SCL decreases.
SCL and SDA
Within the PSU, the SCL and SDA are each
connected to a pull-up resistor. Externally, the
SCL and SDA are connected to the system
through the fault isolation circuit.
Figure 35: Interconnect diagram of SCL and SDA
SCL
SDA
3.3 k
Ω
3.3 k
Ω
3.3 V
MCU
PMBus Communication
Monitoring and Fault Detection
The module communicates with the system over
the PMBus. It provides the monitoring and fault
detection functions.
The module monitors the following:
Module information
Input voltage
Input power
Output voltage
Output power
Baseplate temperature
CNT (On/Off)
The module detects and reports the following:
Input faults
Output overvoltage
Output overcurrent
Baseplate overtemperature
The module communicates with the system over
the PMBus. The following table describes the
PMBus address.
R (ADDR Pull-Down Resistor) Address
Left open
Invalid
200 k
Ω
0x5F
174 k
Ω
0x5E
150 k
Ω
0x5D
124 k
Ω
0x5C
100 k
Ω
0x5B
75 k
Ω
0x5A
49.9 k
Ω
0x59
24.9 k
Ω
0x58
Ground
Invalid
The address bit is as follows.
Bit
7
6
5
4
3
2
1
0
-
Address
Read/Write
Communication will fail if parameter values are
not consistent with those provided in the
following table. Figure 36 shows the timing
diagram of the PMBus interface.
Parameter
Min.
Typ. Max. Unit
Logic input low (V
IL
)
-
-
1.1
V
Logic input high (V
IH
)
2.1
-
-
V
Logic output low (V
OL
) -
-
0.25 V
Logic output high (V
OH
) 2.7
-
-
V
PMBus setup time
100
-
-
ns
PMBus hold-up time
0
-
-
ns
Clock/Data fall time (t
f
) 20+
0.1Cb
-
300 ns
Clock/Data rise time (t
r
)
-
300 ns
Total capacitance of
one bus line (Cb)
-
-
400 pF
