HP Net Vectra, Техническое справочное руководство

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20
2 System Board
Chip-Set
arbitrary order, back-to-back burst reads keep to the 5-2-2-2,5-2-2-2 timing
pattern. When the banks have been filled contiguously (bank A, then bank
B, then bank C), back-to-back burst reads are improved to a 5-2-2-2,3-2-2-2
timing pattern.
IDE Controller
The PCI master/slave IDE controller, supporting four devices, two on each of
two channels, is described on page 26. As well as the traditional five PIO
modes (0 to 4) and three DMA modes (0 to 2), this controller also supports
three Ultra ATA/33, or Ultra DMA, modes (0 to 2), allowing peak transfer
rates up to 33 MB per second.
USB Controller The PCI USB controller, supporting two connectors, is described on page 28.
DMA Controller
The seven channel DMA controller incorporates the functionality of two
82C37 DMA controllers. Channels 0 to 3 are for 8-bit DMA devices, while
channels 5 to 7 are for 16-bit devices (as described on page 57). The
channels can be programmed for any of the four transfer modes: the three
active modes (single, demand, block), can perform three different types of
transfer: read, write and verify. The address generation circuitry can only
support a 24-bit address for DMA devices.
Interrupt Controller
The sixteen channel interrupt controller incorporates the functionality of
two 82C59 interrupt controllers. The two controllers are cascaded, giving 14
external and two internal interrupt sources (as described on page 58).
Counter / Timer
The chip contains a three-channel 82C54 counter/timer. The counters use a
division of the 14.318 MHz OSC input as the clock source.
Super I/O Chip (
NS87317
)
The Super I/O chip is contained within a 160-pin PQFP package. It includes
the following features:
• ACPI register set
• Five Power-On/SCI/SMI channels
• Two SMI channels
• Signal line to an external light
• Power-State bit for PIIX4-based designs.
1book.bk : 1ch02.fb4 Page 20 Wednesday, July 23, 1997 10:17 AM