Rev. 1.10
140
November 04, 2019
Rev. 1.10
141
November 04, 2019
HT45F5Q-3
Battery Charger Flash MCU
HT45F5Q-3
Battery Charger Flash MCU
External Interrupts
The external interrupt is controlled by signal transitions on the pins INT0~INT1. An external
interrupt request will take place when the external interrupt request flags, INT0F~INT1F, is set,
which will occur when a transition, whose type is chosen by the edge select bits, appears on the
external interrupt pins. To allow the program to branch to its respective interrupt vector address,
the global interrupt enable bit, EMI, and respective external interrupt enable bits, INT0E~INT1E,
must first be set. Additionally the correct interrupt edge type must be selected using the INTEG
register to enable the external interrupt function and to choose the trigger edge type. As the external
interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if
their external interrupt enable bit in the corresponding interrupt register has been set and the external
interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also
be setup as an input by setting the corresponding bit in the port control register. When the interrupt
is enabled, the stack is not full and the correct transition type appears on the external interrupt pin,
a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the
external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be
automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the
external interrupt pins will remain valid even if the pin is used as an external interrupt input.
The INTEG register is used to select the type of active edge that will trigger the external interrupt.
A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt.
Note that the INTEG register can also be used to disable the external interrupt function.
Time Base Interrupts
The function of the Time Base Interrupts is to provide regular time signal in the form of an internal
interrupt. They are controlled by the overflow signals from their respective timer functions. When
these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the
program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI
and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack
is not full and the Time Base overflows, a subroutine call to their respective vector locations will
take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will
be automatically reset and the EMI bit will be cleared to disable other interrupts.
The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Its
clock source, f
PSC
, originates from the internal clock source f
SYS
, f
SYS
/4 or f
SUB
and then passes
through a divider, the division ratio of which is selected by programming the appropriate bits in the
TB0C and TB1C registers to obtain longer interrupt periods whose value ranges. The clock source
which in turn controls the Time Base interrupt period is selected using the CLKSEL1~CLKSEL0
bits in the PSCR register.
M
U
X
f
SYS
/4
f
SYS
f
SUB
Prescaler
CLKSEL[1:0]
f
PSC
f
PSC
/2
0
~ f
PSC
/2
7
M
U
X
TB0[2:0]
TB1[2:0]
Time Base 0 Interrupt
Time Base 1 Interrupt
TB0ON
TB1ON
f
PSC
/2
8
~ f
PSC
/2
15
M
U
X
Time Base Interrupts
