3.2 Block Diagrams
3.2.1 Signal Diagrams
ADM ADM ADM ADM ADM ADM ADM ADM
ADM ADM ADM ADM ADM ADM ADM
ABUS-B B.
ABUS-C B.
ABUS-B B.
ABUS-C B.
X-SUS
EVEN SW
X-SCAN
EVEN SW
X-SUS
ODD SW
X-SCAN
ODD SW
POS
RESET
XSUS B.
XBUS B.
XBUS B.
S
DR-
U B.
S
DR-
D B.
Y-SUS
EVEN SW
Y-SCAN
EVEN SW
Y-SUS
ODD SW
Y-SCAN
ODD SW
POS/NEG
RESET
SW
YSUS B.
LVDS
DATA CONVERTER
Gamma
Gain
Error def.
Dither
Memory
Controller
Sub Field
Processor
SCAN CONTROLLER
MPU
TIMMING
ROM
EEPROM
D/A
Conv.
Vsync cont.
Serial comm.
Failure Det.
APC cont.
ANALOG
SW
PSU B.
LOGIC B.
Vcego
Vsago
Vrs
Vra
I
2
C
SIGNAL
INPUT
CN02
CN03
CN04
CN05
CN06
CN07
CN01
CN08
CN05
CN05
CN05
CN05
CN21
CN31
CN34
CN35
CN27
CN26
33
TROUBLESHOOTING THE 50AF1 PANEL
Содержание P50S601/DW3F
Страница 10: ...FINAL WIRING DIAGRAM FOR P50V701 AND P50S601 DW3 9 TABLE OF CONTENTS ...
Страница 11: ...FINAL WIRING DIAGRAM P50X901 DW3 10 TABLE OF CONTENTS ...
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