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9 WINBOND W9425G6EH DDR SDRAM 128M
9.1
General Description
W9425G6EH is a CMOS Double Data Rate synchronous dynamic random access
memory (DDR SDRAM), organized as 4,194,304 words u 4 banks u 16 bits. W9425G6EH
delivers a data bandwidth of up to 500M words per second (-4). To fully comply with the
personal computer industrial standard, W9425G6EH is sorted into the following speed
grades: -4, -5, -5I, -6 and -6I. The -4 is compliant to the DDR500/CL3 and CL4
specification. The -5/-5I is compliant to the DDR400/CL3 specification (the -5I grade
which is guaranteed to support -40°C ~ 85°C). The -6/-6I is compliant to the
DDR333/CL2.5 specification (the -6I grade which is guaranteed to support -40°C ~ 85°C).
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing
reference point for the differential clock is when the CLK and CLK signals cross during a
transition. Write and Read data are synchronized with the both edges of DQS (Data
Strobe). By having a programmable Mode Register, the system can change burst length,
latency cycle, interleave or sequential burst to maximize its performance.
9.2
Features
- 2.5V r0.2V Power Supply for DDR333/400
- 2.6V r0.1V Power Supply for DDR500
- Up to 250 MHz Clock Frequency
- Double Data Rate architecture; two data transfers per clock cycle
- Differential clock inputs (CLK and CLK )
- DQS is edge-aligned with data for Read; center-aligned with data for Write
- CAS Latency: 2, 2.5, 3 and 4
- Burst Length: 2, 4 and 8
- Auto Refresh and Self Refresh
- Precharged Power Down and Active Power Down
- Write Data Mask
- Write Latency = 1
- 7.8μS refresh interval (8K/64 mS refresh)
- Maximum burst refresh cycle: 8
- Interface: SSTL_2
Содержание L32VK06U
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Страница 93: ...FOR ALL PARTS PLEASE MAKE CONTACT WITH ASWO FOR YOUR LOCAL OUTLET GO TO www aswo com ...