K6602743
Rev.2
02.12.’02
- 104 -
Figure 6-13 Initiating an Ultra DMA Write
DMARQ
(device)
DMACK-
(host)
STOP
(host)
DDMARDY-
(device)
HSTROBE
(host)
DD(15:0)
(host)
DA0, DA1, DA2,
CS0-, CS1-
t
UI
t
ACK
t
ENV
t
ZIORDY
t
LI
t
DVS
t
DVH
t
ACK
t
ACK
t
UI
t
DZFS
Note: The definitions for the STOP, DDMARDY and HSTROBE signal lines are not in effect until
DMARQ and DMACK are asserted.
Mode 0(ns) Mode 1(ns) Mode 2(ns) Mode3(ns) Mode4(ns) Mode5(ns)
Description
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
t
DVS
70 48 31 20 6.7 4.8
Data valid setup time at
sender
t
DVH
6.2 6.2 6.2 6.2 6.2 4.8
Data valid hold time at
sender
t
LI
0 150 0 150 0 150 0 100 0 100 0 75
Limited interlock time
t
UI
0 0 0 0 0 0
Unlimited interlock
t
ENV
20 70 20 70 20 70 20 55 20 55 20 50
Envelope time
t
ZIORDY
0 0 0 0 0 0
Minimum time before
driving IORDY
t
ACK
20 20 20 20 20 20
Setup and hold times
before assertion and
negation of DMACK_
t
DZFS
70 48 31 20 6.7 25
Time from data output
released-to-driving until
the first transition of
critical timing
