DP-23, 23G, 24, 27 and 27D CHASSIS MICROPROCESSOR DATA COMMUNICATIONS CIRCUIT DIAGRAM
PAGE 02-04
IOO1
28
31
SCL2
SDA2
SIGNAL PWB
FCEnable
I007
3.3V -> 5V
Level Shift
18
55
PST2
IX01
A/V Select
SCL1
SDA1
29
30
SCL1
SDA1
IOO3
EEPROM
5
6
SDA1
SCL1
Terminal PWB
33
34
5
FCData
51
SDA2
I401
Rainforest
Sweep Cont.
30
31
SCL2
IA01
BBE Control
13
14
IW01
3D-Y/C
4
2
1
SDA1
SCL1
FC Clock
FCData
FC04
FLEX
&
PinP
PFC1
FC Enable
12
11
10
U303
16
14
6
15
Data / Key Out 2
52
4
5
2
Clock / Key Out 1
53
SDA1
SCL1
60
59
IZ01 Sub
Video/Chroma
Y Pr/Pb SW
13
14
IZ02 Main
Video/Chroma
Y Pr/Pb SW
13
14
IX02
Y Pr/Pb
SELECTOR
26
27
SDA2
SCL2
U302
Tuner PinP
U301
Tuner 1 Main
5
SDA2
SCL2
4
4
SCL2
SDA2
5
SDA2
SCL2
PiP
Main
Содержание 43FWX20B
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