Hisense EG59, Техническое руководство, Страница: 10 / 13

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for mixers are generated by VCO divided-by-2 (DCS1800) and divided-
by-4 (GSM850/GSM900). The IF I/Q signals are then filtered and
amplified through a low-pass filter and a PGA. The overall channenl
response composes of an anti-blocking low-pass filter with f3dB =
1.5MHz at mixer differential load and a 5th-order Butterworth low-pass
filter with f3dB = 135kHz. The multi-stage PGA is implemented between
filtering staged to control the gain of the receiver. With a 2dB gain step,
a 60dB dynamic range of the PGA ensures a proper signal level for
baseband setting requirement. Two DC-Offset Corretion (DCOC) loops
ensure that the residual static DC-offset voltage held digitally is less
than 200mV at maxium gain case. DC-offset correction is performed
every time the receiver gain is programmed even in the multislot mode.
4.2. Digital base band circuit principle
4.2.1 General
The digital base band circuit is composed by central control and data
processing unit, power management unit, voice processing unit, display
unit and outside interface unit.
4.2.2 The circuit and principle of each unit
4.2.2.1 Central control and data processing unit
QSC6085 is a single chip integrated multiple processors on-chip. The
baseband circuits and system software incorporates a low-power, high-
performance reduced instruction set chip (RISC) microprocessor core
featuring the ARM926EJ-S™ CPU and Jazelle™ accelerator circuit
from ARM® Limited. There are two low-power, high-performance
QDSP4000™ digital signal processor (DSP) cores, one for the modem
and one for applications.
The QSC6085 is High tier device (153.6kbps data, dual memory bus)
within the family of QUALCOMM single chips. It support all the usual
digital signal processing and software functions, eg : processors,
memory support, video, audio, BREW, security, JTAG. At the same time,
The keypad (and its backlighting), USB, UARTs, RUIM, speakers,
microphones, LCD (and its backlighting), vibration motor are also
supported.