Descriptions and drawings
18/72
Use the following setting if the
NXHXPHYSDR Board
is connected:
X10 PHYSDR
Description
SDRAM_CLK is connected to X3 pin 4
MII_RXD0 to X3 pin 11
SDRAM RAS# is connected to X3 pin 7
Table 18: X10 Setting for NXHXPHYSDR Board at host interface X3
Use the following setting if the
NXHXSDRSPI Board
is connected:
X10 SDRSPI
Description
SDRAM_CLK is connected to X3 pin 4
DPM_DIRQ#/PIO 47 is connected to X3 pin 11
SDRAM RAS# is connected to X3 pin 7
Table 19: X10 Setting for NXHXSDRSPI Board at host interface X3
NXHX 51ETM | Development Board
DOC120606HW06EN | Revision 6 | English | 201501 | Released | Public
© Hilscher 2012 – 2015