Harris HSP50110, Руководство пользователя, Страница: 29 / 32

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Appendix I
Detailed Menu Item Descriptions
Data Path/Modulation Menu
Item 1: Master Clock Frequency
(1,000Hz to 52,000,000Hz)
Enter the frequency of the external reference input clock, or
40,000,000Hz as the frequency of the on-board oscillator.
Make sure that the evaluation board is configured for exter-
nal clock before the external clock is applied to the board.
Item 2: Input Sample Rate
(1,000Hz to 52,000,000Hz)
The input sample rate is the rate that the HSP50110 ENI#
pin (JP1-29) is asserted. In interpolated mode, this should
be an integer submultiple of the master clock. In gated
mode, this is the rate the carrier and bit sync NCOs in the
50110 are updated; in interpolated mode, this is the rate that
the carrier NCO is updated--the bit sync NCO is updated at
the master clock rate. The carrier NCO in the 50210 always
updates at the master clock rate.
Item 3: Input Mode
(0; 1)
Gated = 0; Interpolated = 1.
When the input mode is gated, the new data is processed
when ENI# asserted. Pipelining is done at the master clock
rate. When the input mode is interpolated, new samples are
input when ENI# is asserted, zeros are inserted between
these samples, and the processing is done at the master
clock rate.
Item 4: DQT Input Samples
(0; 1)
Complex = 0; real = 1
If a real input is used (either I or Q only), the unused input
bus should be tied to midscale external to the HSP50110.
This will be 200h if the input format is offset binary and 0 if it
is 2s complement
Item 5: DQT Input Format
(0; 1)
0 = Twos Complement
1 = Offset Binary
Item 6: Carrier Center Freq
(-52,000,000Hz to 52,000,000Hz)
The carrier L.O. center frequency is interpreted as twos
complement, so it can be a positive or negative frequency
and select either the upper or lower sideband of a real input
signal.
Item 7: Data Modulation
(0; 1; 2; 3; 4)
0 = off, 1 = BPSK, 2 = QPSK, 3 = OQPSK, 4 = 8PSK
Item 8: Baud Rate
(1 to 56,000,000 Symbols/s)
This is the output symbol rate of the HSP50210. Note that
entering a value greater than one half the clock rate induces
excessive aliasing.
Item 9: DQT Output Rate
(1 to 56,000,000 Samples/s)
This is the output sample rate of the HSP50110. It will be a
multiple of baud rate and depends on the decimation follow-
ing the HSP50110. If the integrate and dump filtering in the
HSP50210 is enabled, the HSP50110 output rate will be N
times the baud rate where N is the number of samples inte-
grated. If the integrate and dump filtering is not used (and no
external filtering is used, the input rate to the HSP50210
should be 2x the baud.
Item 10: I.F. Noise Bandwidth
(1Hz to 26,000,000Hz)
This is the noise bandwidth of the I.F. filtering preceding the
HSP50110. This is used to compute the gain needed to
compensate for the change in SNR from the A/D to the
matched filtering.
Item 11: DQT Filtering
(0; 1; 2; 3; 4; 5)
0 = Bypass, 1 = I&D, 2 = 3CIC, 3 = I&D w/ comp,
4 = 3CIC w/ comp, 5 = X/SinX
Item 12: DCL RRC Filter
(0; 1) 0 = Bypass; 1 = Enable
The root raised cosine in the HSP50210 should be enabled if
it is the matched filter for the data. It should be bypassed if
the matched filtering is done in the HSP43124 FIR filters. It
can be enabled for out-of-band signal filtering and SNR
improvement when integrate-and-dump filtering over 2 or 4
samples is used. (Some degradation will be seen with inte-
gration over 2 or 4 samples and the RRC filter enabled.)
Item 13: DCL I&D Filtering
(0; 1; 2; 3; 4; 5)
Value 0 < = N < = 5; (2
N
samples integrated)
Item 14: HSP43124 Serial Filter Enable
(0; 1)
0 = HSP43124 filters bypassed
1 = HSP43124 filters enabled
(user is then prompted for a file prefix
prefix.RPT extension assumed)
Item 15: Minimum Es/No
(-100dB to 100dB)
Enter the minimum Es/No expected. This is used to set the
data path maximum gain.
Item 16: Maximum Es/No
(-100dB to 100dB)
Enter the maximum Es/No expected. This is used to set the data
path minimum gain. Enter 100 for noise free.
HSP50110/210EVAL