Hand Held Products IT4000, Руководство по интеграции

Страница: 19 / 56

IMAGETEAM™ 4X00 Series Integration Manual 2 - 9
BLW Beginning of Line. Pixel clock wait 0 to 255. Number of pixel clocks to wait (delay) from the active edge of CIF_LV
(horizontal) to first valid data.
BFW Beginning of Frame Line Wait. 0 to 255 specifies the number of lines to wait from the start of the frame to the first
pixel capture.
LPF Lines Per Frame. 0 to 2047. Actual imager lines per frame = LPF+1 (LPF=imager lines per frame-1).
PCLK_EN Selects if imager is the source of pixel clock. 0=CIF_PCLK is not supplied by sensor (int); 1=CIF_PCLK is supplied
by sensor (ext).
PCP Select the active edge of CIF_PCLK. 0=Data sampled on rising edge of CIF_PCLK; 1=Data sampled on falling
edge of CIF_PCLK.
HSP Horizontal Sync Polarity. 0=CIF_LV is active high, inactive low; 1=CIF_LV is active low, inactive high.
VSP Vertical Sync Polarity. 0=CIF_FV is active high, inactive low; 1=CIF_FV is active low, inactive high.
FR_RATE Frame Capture Rate. Defines the frequency of capture of one video frame (or the number of frames to skip between
captures).
000Capture all incoming frames
001Capture 1 of every 2 frames
010Capture 1 of every 3 frames
011Capture 1 of every 4 frames
100Capture 1 of every 5 frames
101Capture 1 of every 6 frames
110Capture 1 of every 7 frames
111Capture 1 of every 8 frames
Time-out CIF FIFO inactivity time-out interval from 0 to (2
31
-1)
CICR2 - Capture Interface Control Register 2
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Setting 1 0 1 1 1 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X
BLW (Beginning of Line)
ELW (End of Line Wait)
HSW
(Horizontal Sync PW)
Reser
v
ed
BFPW (Beg Fr Pix Wait)
FSW
(fr stbl wt)
CICR3 - Capture Interface Control Register 3
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Setting 0 0 1 0 1 1 0 1 X X X X X X X X X X X X X 0 0 1 1 1 0 1 1 1 1 1
BFW (Beginning of Frame Wait)
EFW (End of Frame Wait) VSW
(Vertical Sync PW)
LPF (Lines Per Frame)
CICR4 - Capture Interface Control Register 4
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Setting X X X X X 0 0 0 1 0 1 1 0 X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0
Reserved
MCLK_DL
Y
PCLK_EN
PCP HSP VSP
MCLK_EN
Reserved
FR_
R
A
T
E
DIV
CITOR - Capture Interface Time-out Register
bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Setting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Time-out