Haier L52A18-A, Руководство пользователя

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5 5
4 4
3 3
2 2
1 1
D
D
C
C
B
B
A
A
14:
Place R500 & R503 termination close to the last part in the daisy chain
For default Bootstrap don't
populate R810 to R813
And Slut JP804 Pin 13 -
1
4
and Pin 17 - 18
19: 17:
Open (Internal ROM on, and mapped to top 32K) Close (Internal ROM off-boot from ext ROM)
18: 13:
NC DDR0 DDR9 DDR15 DDR16 D
DR
18
Open/0 (External Oscillator on TCLK pin) Close/1 (XTAL and Internal Oscillator)
NC
15:
00 = I2C to JTAG Bridge disabled 01 = ICD_SDA on VGA1_SDA, ICD_SCL on VGA1_SCL 10 = ICD_SDA on VGA0_SDA, ICD_SCL on VGA0-SCL 11 = I2C to JTAG bridge disabled, 5 JTAG signals mapped to AVS Pins For General Purpose use
12:
7
:
NC DDR7 DDR10 DDR11 DDR12 DDR8
000 = 20-bit address, 8-bit EXT I/F 001 = 24-bit address, 8-bit EXT I/F 010 = 20-bit address, 16-bit EXT I/F 011 = 24-bit address, 16-bit EXT I/F 1XX = OCM disabled, external parallel control bus (testbench) I2C to JTAG bridge address or General use
Foot Print for a X16 Flash
NC
6:0: 16:
B
O
O
T
S
T
R
A
P
HE
ADE
R
O
PEN
=
0
S
HUNT
E
D
=1
NC R216 R217 R218 R2
19
R220
NC R221 R222 R225 R2
28
ADD
<Doc> <Titl
e
>
C
45
Wednesday, February 15, 2006
Title Siz
e
Document Number
Rev
Date:
S
heet
of
OCMADDR2
OCMDATA9
FSDATA[0..31]
FSBKSEL0
FSADDR7 FSADDR2
OCMADDR19
FSDATA18
/FSWE
OCMDATA2
FSDATA15
FSADDR5
OCMADDR5
OCMDATA7
OCMADDR10
OCMDATA12
FSDATA6
FSADDR5 FSADDR4
FSDATA8
FSDQS1
FSADDR12
FSCKE
FSDATA19
FSDATA9
OCMADDR7
FSDATA21
OCMADDR13
FSDQS0
/RESET
OCMADDR3
FSADDR1
OCMADDR4 OCMADDR9 OCMADDR21
FSDATA0
FSBKSEL1
FSADDR11 FSADDR10
OCMDATA13
/OCM_CS
OCMADDR16
FSADDR6
FSDATA3
OCMDATA4
OCMADDR9
FSDATA25 FSDATA27
/FSCAS
FSDATA17
OCMADDR8
/ROM_CS
FSDATA30
OCMDATA14
FSDATA24
FSADDR8
FSDATA13
FSDQS3
OCMADDR17
OCMDATA10
FSDQS2
FSADDR2
OCMADDR13
OCMDATA8
FSADDR[0..12]
/FSRAS
OCMADDR6 OCMADDR3
FSCLK-FSCLK-
FSCLK-
/OCM_RE
/FSCS0
FSDATA2
OCMADDR14
/BYTE
FSADDR9
FSDATA23
OCMADDR18
OCMDATA6
FSADDR1
FSDATA11
/FSCAS
OCMDATA[0..15]
FSVREF
FSADDR0
OCMADDR12
/RESET
FSADDR6
FSDATA5
OCMADDR15
/OCM_WE
FSADDR0
FSCLK+
FSADDR12
FSCLK-
FSDATA1
OCMADDR5 OCMADDR7 OCMADDR0 OCMADDR15
FSADDR8
FSDQM0
/OCM_RE
FSADDR10 FSADDR11
FSDATA29
OCMADDR1
OCMDATA15
FSDQS0
OCMADDR19
/FSRAS
FSDQM1
OCMADDR12
OCMDATA3
OCMADDR[0..21]
FSDATA14
OCMADDR16
FSDATA28
FSDATA10
OCMADDR20
FSDATA26
FSDQM2
OCMADDR11 OCMADDR2
FSDATA31
OCMADDR8 OCMADDR10
FSBKSEL1
FSDATA22
FSDATA4
OCMADDR11
/OCM_WE
OCMADDR14
FSADDR3
FSDQS3
FSDQM2
FSADDR3
OCMDATA0
OCMADDR17
FSCLK+FSCLK+
FSADDR9
FSDQM3
/FSWE
FSBKSEL0
FSDATA7
OCMADDR6
OCMDATA1
FSCKE
OCMADDR18
OCMDATA5
FSDQM3
OCMADDR1
OCMDATA11
FSADDR4
FSDATA16
FSADDR7
FSDQS2
FSDQM1
OCMADDR4
/FSCS0
FSDQM0
FSCLK+
FSDATA12
FSDATA20
OCMADDR0
FSDQS1
GND
GND
+2.5V_DDR
+2.5V_DDR
+3.3V_I/O
GND
+2.5V_DDR
GND
Flash_Power
FSVREF FSVREF
+3.3V_I/O
FSVREF
+3.3V_I/O
GND
GND
GND
Flash_Power
FSVREF
GND
+3.3V_I/O
+2.5V_DDR
GND
+3.3V_I/O
GND
+3.3V_I/O
GND
+3.3V_I/O
TP
5
0
1
R22 8 10 K
TP
5
2
1
R21 8 10K
TP
5
4
1
R21 7 10K
C234 10 nF
C250 100 nF
R22 9 10 K
C232 10 nF
U15
HY5DU281622CT-4
44 45 24 22 23 21
20 47
29 30 31 32 35 36 37 38 39 40 28 26 27
16
46
53 43
3
9
15
55
61
49
1
18
33
2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65
6
12
58
64
34
48
66
52
14 17 19 25 50
41 42
51
CKE CLK CS CAS RAS WE
NC DM
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP BA0 BA1
NC
CLK
NC NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
VDD
VDD
VDD
DQ0
NC
DQ1
NC
DQ2
NC
DQ3
NC NC
DQ4
NC
DQ5
NC
DQ6
NC
DQ7
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSSQ
NC NC NC NC NC
A11 A12
DQS
R21 6 10K
TP
4
0
R22 2 10 K
R207 10K
C247 22 uF 10 V
U16
HY5DU281622CT-4
44 45 24 22 23 21
20 47
29 30 31 32 35 36 37 38 39 40 28 26 27
16
46
53 43
3
9
15
55
61
49
1
18
33
2 4 5 7 8 10 11 13 54 56 57 59 60 62 63 65
6
12
58
64
34
48
66
52
14 17 19 25 50
41 42
51
CKE CLK CS CAS RAS WE
NC DM
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP BA0 BA1
NC
CLK
NC NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
VDD
VDD
VDD
DQ0
NC
DQ1
NC
DQ2
NC
DQ3
NC NC
DQ4
NC
DQ5
NC
DQ6
NC
DQ7
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSSQ
NC NC NC NC NC
A11 A12
DQS
C230 22 uF
C237 100 nF
R203 0R
RN9 10K
1 8
2 7
3 6
4 5
R21 4 10K
C229 22 uF
10 V
R209 10K
R22 3 10 K
R230 280
TP
4
3
1
TP
4
6
1
C233 100 nF
C238 100 nF
TP
4
9
1
C245 10 nF
C251 2PF
TP
5
1
1
TP
5
3
1
C231 10 nF
U29 Am29LV160D
1 2 3 4 5 6 7 8
18 19 20 21 22 23 24 25
45 43 41 39 36 34 32 30 26 28 11 37 27
17 48
44 42 40 38 35 33 31 29 47 12 15
9
10 13 14 16
46
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
DQ15/A1
DQ14 DQ13 DQ12 DQ11 DQ10
DQ9 DQ8
CE#
OE#
WE#
VCC VSS
A17 A16
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
BYTE#
RESET#
Ready/Busy#
A19 A20 NC /WP_ACC A18
VSS
R22 4 10 K
TP
5
5
1
TP
4
1
1
R231 280
R205 10K
JP1 CON2
1
2
R22 5 10 K
C35 470uF 6V
R206 10K
R22 1 10 K
R208 10K
C246 100 nF
C236 100 nF
R226 10K
C252 2PF
C239 10 nF
R21 5 10K
R204 0R
R22 0 10K
R22 7 10 K
C235 100 nF
TP
4
2
1
TP
4
5
1
R21 9 10K
TP
4
8
1
C249 100 nF
FSDQS[0..3]
3
OCMDATA[0..15]
3
OCMADDR[0..21]
3
FSADDR[0..12]
3
FSBKSEL0
3
/OCM_WE
3
/FSCS0
3
FSBKSEL1
3
FSDATA[0..31]
3
FSCKE
3 FSCLK+
3
/ROM_CS
3
/FSCAS
3
/OCM_RE
3
/FSRAS
3 /FSCS0
3
FSDQM[0..3]
3
/RESET
3
FSCLK-
3 /FSWE
3