Haier HLH26BB, Руководство по обслуживанию

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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PRELIMINARY
Connector for Amtel AT76C112 Video Output
Test pads for DDR
PWM GPIO P_17
I2C Addr
ess:
7C/7D Not Populat
e
d
I2C Address
:
7E/7F
MPU has separate
d
Address/Da
t
a
MPU has Data/Addre
s
s
multiple
x
if not a test pad, an enlarged via
underneath the chip or exposed
trace. Possible DQS MCLK
exposed trace, DQ enlarged via
OUTPUT
MPUGPIO0 MPUCS0N
INPUT
MPUGPIO1 *CS1N MPUGPIO2 MPUGPIO3
0
0
0
0
1
1
1 1
1
1
1
1 1 1
1 1
1
1 1
1
0
0
0
0
*CS1N is not a input or output pin
CS1N=0: SVP-EX CPU access enabled
CS1N=1:SVP-EX CPU access disabled
For EX52 to use
this table
33RX4 TO 100RX4
33RX4 TO 100RX4
R14 MOVED PAGE 5.
30TR04A LCD TV_MAIN A-01
SVP-EX 1 of 2
Qingdao Haier Electronics Co.,Ltd.
B
9 30 Tuesday, July 12, 2005
Title
Size Document Number Rev
Date: Sheet of
MA
0
MA
4
MA
3
MA
7
MA
6
MA
1
1
MA
1
0
MA
2
MA
9
MA
1
MA
5
MA
8
DQ
S
3
DQ
S
2
DQ
S
1
DQ
S
0
DQM0
DQM1
DQM2
DQM3
DQS0
DQM0
MCLK0
AD7
AD6
AD5
AD2
AD3
AD4
AD0
AD1
SDA_EX
SCL_EX
SCL_EX
SDA_EX
P_17
MPUCS0N
MPUCS0N
MPUGPIO4
MPUGPIO4
MPUGPIO1
MPUGPIO0
MPUGPIO1
MPUGPIO2
MPUGPIO3
MPUGPIO0
P_17
MD19
MD4
MD1
MD18
MD11
MD30
MD15
MD10
MD9
MD6
MD2
MD28
MD3
MD14
MD5
MD20
MD0
MD25
MD12
MD31
MD13
MD21
MD16
MD24
MD26
MD8
MD17
MD22
MD29
MD23
MD7
MD27
MD0
A0 A7 A3 A2 A1 A6 A4 A5
MPUGPIO0
MCLK0#
MD[0..31]
MA[0..11]
DQS[0..3]
DQM[0..3]
CAS#
RAS#
CS0#
CLKE
BA0
BA1
MVREF
MCLK0#
MCLK0
A[0..7]
AD[0..7]
RD_EX
WR
ALE
INT#
RST_SVP
WE#
BRT_CNTL
P_39
3V_SDA
3V_SCL
CS
FIELD
MPUGPIO0
E_PWM
VDDMQ
VDDMQ
VDDM VCC
VDDH3_3 VDDH3_3
VD3_3
VDDH3_3
VDDMQ
5V-1_CPU
R14 0R
C6
100nF
R3 0R_DNS
RP1
100Rx4
1
2
3
4
8
7
6
5
RP2 100Rx4
1
2
3
4
8
7
6
5
C4
68pF
R17 0R
R21
1K
R8 0R_DNS
C3
100pF
R16
1K
C5
68pF
R4 0R_DNS
TP4
TP_T_C30
RP
4
3
100R
x
4
1 2 3 4
8 7 6 5
R19
10K_DNS
TP1
TP_T_C30
TP3
TP_T_C30
R10 68R TP25
TP_T_C30
R20
10K_DNS
R1
1K5
R6 10R
R15
10K_DNS
C305
100nF
R9 68R
C306
100nF
TP2
TP_T_C30
C307
100nF
C308
100nF
C309
100nF
R5 4K7
+
C1
10uF/16V
TP5
TP_T_C30
C310
100nF
RP
4
2
100R
x
4
1 2 3 4
8 7 6 5
C312
100nF
Q1
MMBT3904
1
2
3
R2
4K7
C316
100nF
C2
100nF
C314
100nF
TP24
TP_T_C30
C315
100nF C317
100nF C313
100nF
C318
100nF C320
100nF
C311
100nF
R18
10K
C319
100nF
SVP-EX [256]
(1 of 2)
U1A
SVP-EX_256
73
75
76
78
84
86
88
90
91
93
94
96
102
104
106
108
148
150
152
154
160
162
163
165
166
168
170
172
178
180
181
183
79
97
159
177
82 100 156 174 109 111 112 114 115 117 118 120 122 123 125 126 130 131 133 135 137 138 140
142
144
145
147
193 191 139 141 179 171 161 153 136 134 124 119 103 95 85 77 173 169 155 151 132 129 121 116 105 101 87 83 81 80
13
12
15
16
14
203
202
201
200
197
196
195
194
216
217
218
219
220
18
17
98 99 157 158 176 175 190 189 188 192
206 207 208 209 210 211 212 213
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
DQM0
DQM1
DQM2
DQM3
DQ
S
0
DQ
S
1
DQ
S
2
DQ
S
3
MA
1
1
MA
1
0
MA
9
MA
8
MA
7
MA
6
MA
5
MA
4
MA
3
MA
2
MA
1
MA
0
MCK
0
MCK
0
#
CS
0
#
CS
1
#
R
AS#
C
AS#
MV
RE
F
WE#
CLKE
BA0
BA1
MP
UG
P
IO
0
MP
UG
P
IO
1
V
DDR
VSSR
V
DDM
V
DDM
V
DDM
V
DDM
V
DDM
V
DDM
V
DDM
V
DDM
V
DDM
V
DDM
V
DDM
V
DDM
VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM VSSM V
DDM
VSSM
RESET
TESTMODE
V5SF
SDA
SCL
A_D7
A_D6
A_D5
A_D4
A_D3
A_D2
A_D1
A_D0
RD#
WR#
ALE
MPUCS0N
INT#
FLD/IO
P_17
VSSM V
DDM
V
DDM
VSSM VSSM V
DDM
MP
UG
P
IO
2
MP
UG
P
IO
3
MP
UG
P
IO
4
NC
A
DDR0
A
DDR1
A
DDR2
A
DDR3
A
DDR4
A
DDR5
A
DDR6
A
DDR7
TP6
TP_T_C30
R7
10K
R12
10K
R13
4K7