Haier HL40BG - 40" LCD TV, Руководство по обслуживанию

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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BCM_DDR_ADDR0
BCM_DDR_ADDR1
BCM_DDR_ADDR2
BCM_DDR_ADDR3
BCM_DDR_ADDR4
BCM_DDR_ADDR5
BCM_DDR_ADDR6
BCM_DDR_ADDR7
BCM_DDR_ADDR8
BCM_DDR_ADDR9
BCM_DDR_ADDR10
BCM_DDR_ADDR11
BCM_DDR_BA0
BCM_DDR_BA1
BCM_DDR_DQ0
BCM_DDR_DQ1
BCM_DDR_DQ2
BCM_DDR_DQ3
BCM_DDR_DQ4
BCM_DDR_DQ5
BCM_DDR_DQ6
BCM_DDR_DQ7
BCM_DDR_DQ8
BCM_DDR_DQ9
BCM_DDR_DQ10
BCM_DDR_DQ11
BCM_DDR_DQ12
BCM_DDR_DQ13
BCM_DDR_DQ14
BCM_DDR_DQ15
BCM_DDR_DQ16
BCM_DDR_DQ17
BCM_DDR_DQ18
BCM_DDR_DQ19
BCM_DDR_DQ20
BCM_DDR_DQ21
BCM_DDR_DQ22
BCM_DDR_DQ23
BCM_DDR_DQ24
BCM_DDR_DQ25
BCM_DDR_DQ26
BCM_DDR_DQ27
BCM_DDR_DQ28
BCM_DDR_DQ29
BCM_DDR_DQ30
BCM_DDR_DQ31
BCM_DDR_DQM0
BCM_DDR_DQM1
BCM_DDR_DQM2
BCM_DDR_DQM3
BCM_DDR_DQS0
BCM_DDR_DQS1
BCM_DDR_DQS2
BCM_DDR_DQS3
BCM_DDR_RASb
BCM_DDR_CASb
BCM_DDR_WEb
BCM_DDR_CS0b
BCM_DDR_CKE
BCM_DDR_CLK0
BCM_DDR_CLK0b
BCM_DDR_BA0 MEM_DDR_BA0
BCM_DDR_BA1 MEM_DDR_BA1
BCM_DDR_ADDR10
BCM_DDR_ADDR0 MEM_DDR_ADDR10
MEM_DDR_ADDR0
BCM_DDR_ADDR1 MEM_DDR_ADDR1
BCM_DDR_ADDR2 MEM_DDR_ADDR2
BCM_DDR_ADDR3
BCM_DDR_ADDR4 MEM_DDR_ADDR3
MEM_DDR_ADDR4
BCM_DDR_ADDR5 MEM_DDR_ADDR5
BCM_DDR_ADDR6 MEM_DDR_ADDR6
BCM_DDR_ADDR7
BCM_DDR_ADDR8 MEM_DDR_ADDR7
MEM_DDR_ADDR8
BCM_DDR_ADDR9 MEM_DDR_ADDR9
BCM_DDR_ADDR11 MEM_DDR_ADDR11
BCM_DDR_ADDR12
BCM_DDR_CKE MEM_DDR_ADDR12
MEM_DDR_CKE
BCM_DDR_CLK0b
BCM_DDR_CLK0
DDR_VREF0
DDR_VREF1
MEM_DDR_DQ7
MEM_DDR_DQ5
BCM_DDR_DQ7
BCM_DDR_DQ5
BCM_DDR_DQ3
MEM_DDR_DQ1
MEM_DDR_DQ2
MEM_DDR_DQ4
BCM_DDR_DQ1
BCM_DDR_DQ4
MEM_DDR_DQ0
MEM_DDR_DQ15
BCM_DDR_DQ0
BCM_DDR_DQ15
MEM_DDR_DQ12
MEM_DDR_DQ10
MEM_DDR_DQ8
BCM_DDR_DQ12
BCM_DDR_DQ10
BCM_DDR_DQ8
MEM_DDR_DQ9
MEM_DDR_DQ13
MEM_DDR_DQ11
BCM_DDR_DQ9
BCM_DDR_DQ11
MEM_DDR_DQ23
MEM_DDR_DQ21
MEM_DDR_DQ19
BCM_DDR_DQ23
BCM_DDR_DQ21
BCM_DDR_DQ19
MEM_DDR_DQ17
MEM_DDR_DQ18
MEM_DDR_DQ20
BCM_DDR_DQ17
BCM_DDR_DQ18
BCM_DDR_DQ22
MEM_DDR_DQ16
MEM_DDR_DQ31
BCM_DDR_DQ16
BCM_DDR_DQ31
MEM_DDR_DQ28
MEM_DDR_DQ26
MEM_DDR_DQ24
BCM_DDR_DQ28
BCM_DDR_DQ26
BCM_DDR_DQ24
MEM_DDR_DQ25
MEM_DDR_DQ29
MEM_DDR_DQ27
BCM_DDR_DQ25
BCM_DDR_DQ29
BCM_DDR_DQ27
MEM_DDR_DQS0 BCM_DDR_DQS0
MEM_DDR_DQS1 BCM_DDR_DQS1
MEM_DDR_DQS2 BCM_DDR_DQS2
MEM_DDR_DQS3 BCM_DDR_DQS3
MEM_DDR_DQ3
MEM_DDR_ADDR5
MEM_DDR_ADDR12
MEM_DDR_ADDR11
MEM_DDR_ADDR10
MEM_DDR_ADDR9
MEM_DDR_ADDR8
MEM_DDR_ADDR7
MEM_DDR_ADDR4
MEM_DDR_ADDR3
MEM_DDR_ADDR2
MEM_DDR_ADDR1
MEM_DDR_ADDR0
MEM_DDR_ADDR6
MEM_DDR_BA1
MEM_DDR_BA0
MEM_DDR_CS0b
MEM_DDR_CLK0
MEM_DDR_CKE
MEM_DDR_DQ15
MEM_DDR_DQ14
MEM_DDR_DQ13
MEM_DDR_DQ12
MEM_DDR_DQ11
MEM_DDR_DQ10
MEM_DDR_DQ9
MEM_DDR_DQ8
MEM_DDR_DQ7
MEM_DDR_DQ6
MEM_DDR_DQ5
MEM_DDR_DQ4
MEM_DDR_DQ3
MEM_DDR_DQ2
MEM_DDR_DQ1
MEM_DDR_DQS0
MEM_DDR_DQS1
MEM_DDR_DQ0
MEM_DDR_DQM0
MEM_DDR_DQM1
MEM_DDR_WEb
MEM_DDR_CASb
MEM_DDR_RASb
MEM_DDR_ADDR5
MEM_DDR_ADDR12
MEM_DDR_ADDR11
MEM_DDR_ADDR10
MEM_DDR_ADDR9
MEM_DDR_ADDR8
MEM_DDR_ADDR7
MEM_DDR_ADDR4
MEM_DDR_ADDR3
MEM_DDR_ADDR2
MEM_DDR_ADDR1
MEM_DDR_ADDR0
MEM_DDR_ADDR6
MEM_DDR_BA1
MEM_DDR_BA0
MEM_DDR_CKE
MEM_DDR_CLK0
MEM_DDR_CS0b
MEM_DDR_WEb
MEM_DDR_CASb
MEM_DDR_RASb
MEM_DDR_DQS2
MEM_DDR_DQS3
MEM_DDR_DQM2
MEM_DDR_DQM3
MEM_DDR_DQ17
MEM_DDR_DQ16
MEM_DDR_DQ19
MEM_DDR_DQ18
MEM_DDR_DQ21
MEM_DDR_DQ20
MEM_DDR_DQ23
MEM_DDR_DQ22
MEM_DDR_DQ25
MEM_DDR_DQ24
MEM_DDR_DQ27
MEM_DDR_DQ26
MEM_DDR_DQ29
MEM_DDR_DQ28
MEM_DDR_DQ31
MEM_DDR_DQ30
DDR_VREF1
DDR_VREF0
BCM_DDR_RASb
BCM_DDR_WEb MEM_DDR_WEb
BCM_DDR_CS0b
MEM_DDR_CASb
MEM_DDR_CS0b
MEM_DDR_RASb
BCM_DDR_CASb
BCM_DDR_ADDR12
BCM_DDR_DQ2
BCM_DDR_DQ6
BCM_DDR_DQ14
BCM_DDR_DQ13
BCM_DDR_DQ30
MEM_DDR_DQ6
MEM_DDR_DQ14
BCM_DDR_DQ20
MEM_DDR_DQ22
MEM_DDR_DQ30
DDR_CLK_TEST
MEM_DDR_CLK0
MEM_DDR_CLK0b
MEM_DDR_CLK0b
MEM_DDR_CLK0b
BCM_DDR_DQM0
BCM_DDR_DQM1
BCM_DDR_DQM2
BCM_DDR_DQM3
MEM_DDR_DQM2
MEM_DDR_DQM3
MEM_DDR_DQM0
MEM_DDR_DQM1
D2.6V_BCM3560
D2.6V_BCM3560
D2.6V_BCM3560
D2.6V_BCM3560
D2.6V_BCM3560
D2.6V_BCM3560
D2.6V_BCM3560
D2.6V_BCM3560
Title
Size Document Number Rev
Date: Sheet of
<Doc> ?
<Title>
C
12 18 Tuesday, November 07, 2006
Title
Size Document Number Rev
Date: Sheet of
<Doc> ?
<Title>
C
12 18 Tuesday, November 07, 2006
Title
Size Document Number Rev
Date: Sheet of
<Doc> ?
<Title>
C
12 18 Tuesday, November 07, 2006
New DDR routing rules:
------------------------------
All timing is relative the CLK/CLKb that arrive at the destination DDR SDRAM chip.
1) X = CLK/CLKb should be a matched differential pair with a length < 4"
2) Address and control should be X +/- 0.75" (or 100 ps)
3) DQS and DQM should be X +/- 0.75" (or 100 ps)
4) All DQs should match corresponding byte lane DQS/DQMs /- 0.20" (or 30 ps)
5) Place 22 ohm resistors for DQ and DQS bidirectional lines half-way between BCM and Memory.
6) Place 22 ohm resistors for CLK, ADDR, BA, DM, RAS, CAS, WE, CKE output-only lines near BCM.
7) Place DDR_VREF[2:1] resistor dividers near BCM.
8) Trace impedances should be 60 to 65 ohms
9) Route DDR_VREF[2:1] with 30-mil trace and at least 1 high quality ceramic bypass capacitor for each
connection to a device.
10) All traces should have a >= 3 to 1 spacing ratio from the reference GND/PWR layer. (e.g. 15 mil
line-to-line spacing for a 5 mil dielectric thickness)
Route clocks as differential pairs
Place Cap Close
to Memory VREF
Place all these TPs near BCM3560,
inside socket border.
Place Cap Close
to Memory VREF
Try to place decoupling capacitors on the
same side of the PCB as the DDR to reduce
the inductance caused by using vias.
Try to place decoupling capacitors on the
same side of the PCB as the DDR to reduce
the inductance caused by using vias.
Byte lanes swapped to optimize layout
PROPRIETARY
CONFIDENTIAL
Place these 5 resistors at
the end of the clock lines
Place these 5 resistors at
the end of the clock lines
1
2
3
4 5
6
7
8
RN37 22 RN37 22
+
C99 100uF
10V
+
C99 100uF
10V
C357
470pF
C357
470pF
R131 22 R131 22
+
C100 100uF
10V
+
C100 100uF
10V
1
2
3
4 5
6
7
8
RN31 22 RN31 22
R
4
8
5
2
4
3
(
D
N
I)
1
%
R
4
8
5
2
4
3
(
D
N
I)
1
%
DDR0_ADDR00
K3
DDR0_ADDR01
K2
DDR0_ADDR02
K5
DDR0_ADDR03
K6
DDR0_ADDR04
L3
DDR0_ADDR05
L2
DDR0_ADDR06
M2
DDR0_ADDR07
M1
DDR0_ADDR08
L4
DDR0_ADDR09
L5
DDR0_ADDR10
K4
DDR0_ADDR11
L6
DDR0_ADDR12
M3
DDR0_BA0
J1
DDR0_BA1
J2
DDR0_CAS
H2
DDR0_CKE
M4
DDR0_CLK0
N1
DDR0_CLK0
N2
DDR0_CS0
J4
DDR0_DATA00
R2
DDR0_DATA01
R3
DDR0_DATA02
P6
DDR0_DATA03
T1
DDR0_DATA04
R4
DDR0_DATA05
T2
DDR0_DATA06
T3
DDR0_DATA07
R5
DDR0_DATA08
N3
DDR0_DATA09
M5
DDR0_DATA10
P1
DDR0_DATA11
M6
DDR0_DATA12
P2
DDR0_DATA13
N4
DDR0_DATA14
P3
DDR0_DATA15
R1
DDR0_DATA16
F2
DDR0_DATA17
F1
DDR0_DATA18
H3
DDR0_DATA19
G3
DDR0_DATA20
J6
DDR0_DATA21
G2
DDR0_DATA22
J5
DDR0_DATA23
G1
DDR0_DATA24
D2
DDR0_DATA25
F4
DDR0_DATA26
D1
DDR0_DATA27
F3
DDR0_DATA28
E3
DDR0_DATA29
G5
DDR0_DATA30
E2
DDR0_DATA31
E1
DDR0_DM0
P4
DDR0_DM1
N6
DDR0_DM2
H5
DDR0_DM3
H6
DDR0_DQS0
P5
DDR0_DQS1
N5
DDR0_DQS2
H4
DDR0_DQS3
G4
DDR0_RAS
J3
DDR0_VREF0
U2
DDR0_VREF1
C1
DDR0_WE
H1
DDR_CLK_TEST
F5
D
D
R
-S
D
R
A
M
U22C
BCM3551KPB5G
BGA676_35X35
D
D
R
-S
D
R
A
M
U22C
BCM3551KPB5G
BGA676_35X35
C398 2700pF C398 2700pF
R522
4.99K-1%
1%
R522
4.99K-1%
1%
R407
243 (DNI)
1%
R407
243 (DNI)
1%
1
2
3
4 5
6
7
8
RN28 22 RN28 22
C295 0.1uF C295 0.1uF
C406 2700pF C406 2700pF
C319 0.1uF C319 0.1uF
R231 22 R231 22
R
4
8
6
2
4
3
(
D
N
I)
1
%
R
4
8
6
2
4
3
(
D
N
I)
1
%
C369
1uF
C369
1uF
TP22 TP22
C110
0.1uF
C110
0.1uF
1
2
3
4 5
6
7
8
RN33 22 RN33 22
R
4
1
5
2
4
3
(
D
N
I)
1
%
R
4
1
5
2
4
3
(
D
N
I)
1
%
C71
0.1uF
C71
0.1uF
1
2
3
4 5
6
7
8
RN24 22 RN24 22
R
5
0
6
2
4
3
(
D
N
I)
1
%
R
5
0
6
2
4
3
(
D
N
I)
1
%
R132
4.99K-1%
1%
R132
4.99K-1%
1%
C349 470pF C349 470pF
1
2
3
4 5
6
7
8
RN25 22 RN25 22
R
4
1
6
2
4
3
(
D
N
I)
1
%
R
4
1
6
2
4
3
(
D
N
I)
1
%
C288 470pF C288 470pF
1
2
3
4 5
6
7
8
RN30 22 RN30 22
R152 22 R152 22
A0
29
A1
30
A2
31
A3
32
A4
35
A5
36
A6
37
A7
38
A8
39
A9
40
A10/AP
28
A11
41
A12
42
BA0
26
BA1
27
CAS
22
CLK
45
CLK
46
(IN) UDM
47
UDQS
51
RAS
23
WE
21
V
D
D
3
3
V
D
D
1
V
D
D
1
8
V
D
D
Q
9
V
D
D
Q
1
5
V
D
D
Q
3
V
D
D
Q
5
5
V
D
D
Q
6
1
VREF
49
V
S
S
3
4
V
S
S
4
8
V
S
S
6
6
V
S
S
Q
6
V
S
S
Q
5
8
V
S
S
Q
1
2
V
S
S
Q
6
4
V
S
S
Q
5
2
DQ0
2
DQ1
4
DQ2
5
DQ3
7
DQ4
8
DQ5
10
DQ6
11
DQ7
13
DQ8
54
DQ9
56
DQ10
57
DQ11
59
DQ12
60
DQ13
62
DQ14
63
DQ15
65
LDQS
16
(IN) LDM
20
CS
24
CKE
44
A13/NC
17
256Mbit
DDR
SDRAM
16Mx16
U16
MT46V16M16TG-5B
TSOP66
256Mbit
DDR
SDRAM
16Mx16
U16
MT46V16M16TG-5B
TSOP66
1
2
3
4 5
6
7
8
RN7 22 RN7 22
R135 22 R135 22
1
2
3
4 5
6
7
8
RN34 22 RN34 22
C79
1uF C79
1uF
1
2
3
4 5
6
7
8
RN5 22 RN5 22
R
5
0
7
2
4
3
(
D
N
I)
1
%
R
5
0
7
2
4
3
(
D
N
I)
1
%
C112
470pF
C112
470pF
R
4
0
9
2
4
3
(
D
N
I)
1
%
R
4
0
9
2
4
3
(
D
N
I)
1
%
C256
470pF
C256
470pF
C254 1000pF C254 1000pF
R147 22 R147 22
C75
470pF
C75
470pF
C396 0.047uF C396 0.047uF
1
2
3
4 5
6
7
8
RN4 22 RN4 22
C397 0.047uF C397 0.047uF
1
2
3
4 5
6
7
8
RN36 22 RN36 22
R470
243 (DNI)
1%
R470
243 (DNI)
1%
C127
10uF
C127
10uF
R523
4.99K-1%
1%
R523
4.99K-1%
1%
A0
29
A1
30
A2
31
A3
32
A4
35
A5
36
A6
37
A7
38
A8
39
A9
40
A10/AP
28
A11
41
A12
42
BA0
26
BA1
27
CAS
22
CLK
45
CLK
46
(IN) UDM
47
UDQS
51
RAS
23
WE
21
V
D
D
3
3
V
D
D
1
V
D
D
1
8
V
D
D
Q
9
V
D
D
Q
1
5
V
D
D
Q
3
V
D
D
Q
5
5
V
D
D
Q
6
1
VREF
49
V
S
S
3
4
V
S
S
4
8
V
S
S
6
6
V
S
S
Q
6
V
S
S
Q
5
8
V
S
S
Q
1
2
V
S
S
Q
6
4
V
S
S
Q
5
2
DQ0
2
DQ1
4
DQ2
5
DQ3
7
DQ4
8
DQ5
10
DQ6
11
DQ7
13
DQ8
54
DQ9
56
DQ10
57
DQ11
59
DQ12
60
DQ13
62
DQ14
63
DQ15
65
LDQS
16
(IN) LDM
20
CS
24
CKE
44
A13/NC
17
256Mbit
DDR
SDRAM
16Mx16
U26
MT46V16M16TG-5B
TSOP66
256Mbit
DDR
SDRAM
16Mx16
U26
MT46V16M16TG-5B
TSOP66
1
2
3
4 5
6
7
8
RN29 22 RN29 22
C87
10uF
C87
10uF
R218 22 R218 22
C286 0.01uF C286 0.01uF
R125
4.99K-1%
1%
R125
4.99K-1%
1%
C351 0.01uF C351 0.01uF
C255 1000pF C255 1000pF
R
4
1
0
2
4
3
(
D
N
I)
1
%
R
4
1
0
2
4
3
(
D
N
I)
1
%
1
2
3
4 5
6
7
8
RN2 22 RN2 22
1
2
3
4 5
6
7
8
RN27 22 RN27 22