GRUNDIG Service
GDP 2200
2 - 13
Name
Type
Pin
Description AML3250
SDRAM1 (MPEG)
m1_a[10:0]
O
*
Adress bus, pins: 16…19, 21, 22, 24, 25, 27…30
m1_ba
O
15
Bank select
m1_cas_n
O
32
Column adress strobe
m1_clko
O
174
Clock
m1_cs_n[0]
O
34
Chip select 0
m1_cs_n[1]
O
35
Chip select 1
m1_d[15:0]
B
*
SDRAM data bus, pins: 162…164, 166…168, 170…172, 176…178, 180…182, 184
m1_dqm
O
14
Input / output mask
m1_ras_n
O
33
Row address strobe
m1_we_n
O
13
Write enable
SDRAM2
(Host Memory)
m2_a[11:0]
B
*
Adress bus, pins: 134,135, 137…140, 142…146, 148
These signals are also used to configure the chip at reset.
m2_ba0
O
133
Bank select. Also used as a chip select when the decoder is configured to interface to static RAMs.
m2_cas_n
O
152
Column address strobe
m2_clko
B
130
Clock
m2_d[15:0]
B
*
Data bus, pins: 108…111, 113…117, 119…123, 125, 126
m2_dqm[1:0]
O
149, 150
Input / output mask
m2_scs0_n
O
132
SDRAM chip select. This signal is low when the SDRAM is selected.
m2_ecs_n
O
128
EPROM chip select. This signal is low when the EPROM is selected.
m2_eoe_n
O
127
EPROM output enable
m2_ras_n
O
151
Row address strobe
m2_we_n
O
153
write enable (active low)
GPIO / External
Interface
ad[7:0]
B
83…87, 92…94
External interface data, GPIO[7:0]
as
B
95
Address strobe, GPIO[8]
cs_n
B
96
Chip select, GPIO[11]
wait_n
B
97
Wait, GPIO[12]
wrn_rwn
B
98
Intel processor: WR_n, Motorola R/W_n, GPIO[10]
rdn_e
B
99
Intel Processor: RD_n, Motorola (E)nable, GPIO[9]
wclk
B
100
Wait clock, GPIO[13]
x_int
B
101
Interrupt, GPIO[14]
IC-Blockdiagramme / IC Block Diagrams
AML3250
