Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams
DVD-Kit1
3 - 4
GRUNDIG Service
PIN NAME
TYPE
DESCRIPTION
1
PWDN
Digital input
Powerdown control; low is ON, high is POWER OFF; Internal pull-down
2
SCKI
Digital input
System clock input (256 or 384fs)
3
TEST
Digital output
Reserved
4
ML/I2S
Digital input
Latch enable (software mode) or input format selection (hardware mode); Internal pull-up
5
MC/IWL
Digital input
Serial control data clock input (software mode) or input word length selection (hardware mode); Internal pull-up
6
MD/DM
Digital input
Serial control data input (software mode) or de-emphasis selection (hardware mode); Internal pull-up
7
RSTB
Digital input
Reset input – active low; Internal pull-up
8
ZERO
Digital output
Infinite zero detect – active low; Open drain type output with active pull-down
9
VOUTR
Analogue output
Right channel DAC output
10
AGND
Supply Analogue
ground supply
11
AVDD
Supply Analogue
positive supply
12
VOUTL
Analogue output
Left channel DAC output
13
CAP
Analogue output
Analogue internal reference
14
BCKIN
Digital input
Audio data bit clock input
15
DIN
Digital input
Serial audio data input
16
LRCIN
Digital input
Sample rate clock input
17
MUTE
Digital IO
Mute control pin, input or automute output; Low is not mute, high is mute, Z is automute
18
MODE
Digital input
Mode select pin; Low is software mode, high is hardware control; Internal pull-down
19
DVDD
Supply Digital
positive supply
20
DGND
Supply Digital
ground supply
SERIAL
INTERFACE
DIGITAL
FILTERS
CONTROL INTERFACE
BCKIN (14)
(9) VOUTR
(12) VOUTL
SIGMA
DELTA
MODULATOR
MUTE/
ATTEN
(20)
DGND
(10)
AGND
(13)
CAP
(11)
AVDD
(19)
DVDD
LRCIN (16)
DIN (15)
(3) TEST
(8) ZERO
256fs/384fs
MUTE
(17)
MODE
(18)
RSTB
(7)
PWDN
(1)
MD/DM
(6)
MC/IWL
(5)
ML/I2S
(4)
SCKI
(2)
DAC
SIGMA
DELTA
MODULATOR
MUTE/
ATTEN
DAC
WM8720
WM8720
16
15
14
20
19
18
17
5
6
7
1
2
3
4
BCKIN
DIN
LRCIN
MUTE
MODE
DGND
DVDD
RSTB
MD/DM
MC/IWL
ML/I2S
TEST
PWDN
SCKI
13
12
11
8
9
10
AVDD
VOUTL
CAP
AGND
VOUTR
ZERO
WM8720
INT
0
–
CNTR
0
CNTR
1
V
REF
AV
SS
RAM
ROM
C P U
A
X
Y
S
PC
H
PC
L
PS
V
SS
21
RESET
18
V
CC
1
15
CNV
SS
2
3
X
IN
19
20
SI/O(8)
Reset input
Clock generating
circuit
A-D
converter
(10)
Timer Y( 8 )
Timer X( 8 )
Prescaler 12(8)
Prescaler X(8)
Prescaler Y(8)
Timer 1( 8 )
Timer 2( 8 )
Sub-clock
Main-clock
input
X
OUT
X
CIN
X
COUT
output
Watchdog
timer
Reset
P2(8)
P3(5)
I/O port P2
I/O port P3
P4(5)
I/O port P4
I C
INT
3
4
6
8
5
7
39
41
38
40
42
9
11
13
17
10
12
14 16
P1(8)
I/O port P1
22
24
26
28
23
25
27
29
P0(8)
I/O port P0
30 31 32 3334 35 36 37
PWM
(8)
2
X
CIN
X
COUT
P4
0
/CNTR
1
P4
1
/INT
0
P4
2
/INT
1
P4
3
/INT
2
AV
SS
P4
4
/INT
3
/PWM
V
REF
V
CC
P3
1
/AN
1
P3
2
/AN
2
P0
0
P0
4
P0
5
P0
6
P0
7
P1
1
P1
2
P1
3
/(LED
0
)
P1
4
/(LED
1
)
P1
5
/(LED
2
)
P1
0
P0
1
P0
2
P3
0
/AN
0
P3
3
/AN
3
P3
4
/AN
4
P0
3
40
41
42
22
23
24
25
26
27
28
29
30
31
32
34
35
36
37
38
39
33
3
2
1
21
20
19
18
17
16
15
14
13
12
11
9
8
7
6
5
4
10
M38513M4-XXXFP
M38513M4-XXXSP
P1
6
/(LED
3
)
P1
7
/(LED
4
)
P2
7
/CNTR
0
/S
RDY
P2
6
/S
CLK
P2
5
/SCL
2
/TxD
P2
4
/SDA
2
/RxD
P2
3
/SCL
1
P2
2
/SDA
1
CNV
SS
P2
1
/X
CIN
P2
0
/X
COUT
RESET
X
IN
X
OUT
V
SS
M38513