4
SMS 8301A Component Analog Video to Serial Component Digital Converter
Signal Processing
The three video input channels (Y/G, B-Y/B, R-Y/R) are passed
through Analog Processing and Filtering circuitry then applied to
the Analog–to–Digital Converter and Digital Filter block.
Three A/D converters sample the video at 27MHz and converts it
to 10–bit data.
In GBR input mode, the Digital Matrix combines the input
channels to produce color difference signals required by
downstream circuitry. If the input is already color difference, the
combining circuitry is bypassed. Out of the matrix, the B–Y and
R–Y channels are applied to the Chroma Channel Lowpass Filters;
the Y channel is applied to a delay circuit.
The digital filters lowpass filter the B–Y and R–Y channels. Two
filters alternately drive a common bus to create a multiplexed
chroma channel data stream.
The Y Channel Delay delays the Y signal to compensate for the
delay introduced into the B–Y and R–Y channels by the Chroma
Channel Lowpass Filters.
The Calibration Display Generator uses the delayed Y channel
and the multiplexed B–Y and R–Y channels to produce a signal
which can be observed on an oscilloscope connected at the
module front panel. The resulting display contains all three
channels and calibration markers for each.
The Blanking Gate, Limiter and Rounder receives delayed Y data
and the multiplexed B–Y, R–Y channel data. It rounds 11-bit input
data to 10 or 8 bits as required and adds digital blanking level data
as required.
The CCIR601 Encoder receives the Y and Chroma outputs of the
Blanking Gate, Limiter and Rounder and creates a SMPTE 125M/
CCIR601 format, parallel data output.
The Scrambler and Serializer receives the multiplexed CCIR601
(SMPTE 125M) data stream from the CCIR601 Encoder and
produces serial outputs conforming to the proposed SMPTE
259M/ EBU Tech 3267 standard.
347301A1.book Page 4 Thursday, November 2, 2000 10:41 AM
