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8914 Instruction Manual

Adjustments, Testpoints, and Indicators

Delay Adjustments

Signal delay for each channel is set by two 16-position rotary switches that
provide additive coarse and

ne adjustments. The amount of both the

inherent delay of the signal path and the increments of induced delay
varies according to signal data rate.

Table 1

provides delay

gures for the

three accepted AES data rates—48 KHz, 44.1 KHz, and 32 KHz.

48 KHz Input Signal Example

Inherent (minimum) circuit delay with no set delay adjustment (rotary
switches at 0, 0) is 1.2 ms. Any switch setting above 0,0 masks the inherent
delay and, starting at 2 ms, adds the selected number of delay increments.

For example, setting Coarse to 0 and Fine to 1 produces 2 ms of delay. Each
additional Fine switch increment adds 2 ms.

Setting Coarse to 1 and Fine to 0 produces 32 ms of delay. Each additional
Coarse switch increment adds 32 ms.

Table 1. Delay Adjustment Settings

Input

Signal

Minimum Delay

(switches @ 0,0)

Adjustment

Increment

Incremental

Delay Range

48 KHz

1.2 ms

Fine

2 ms (96 frames)

2 ms to 510 ms

Coarse

32 ms (8 blocks)

44.1 KHz

1.305 ms

Fine

2.177 ms (96 frames)

2.177 ms to 555.9 ms

Coarse

34.88 ms (8 blocks)

32 KHz

1.799 ms

Fine

3 ms (96 frames)

3 ms to 765 ms

Coarse

48 ms (8 blocks)

Содержание 8914 -

Страница 1: ...8914 D U A L AES EBU DELAY DISTRIBUTION AMPLIFIER Instruction Manual 071 0547 01 FIRST PRINTING JANUARY 1999 REVISED PRINTING APRIL 1999 ...

Страница 2: ...nts issued and pending Product options and specifications subject to change without notice The informa tion in this manual is furnished for informational use only is subject to change without notice and should not be construed as a commitment by Grass Valley Group Grass Valley Group assumes no re sponsibility or liability for any errors or inaccuracies that may appear in this publication Region Vo...

Страница 3: ...lifier Introduction 1 Module Installation 2 Cabling 3 Inputs 3 Outputs 4 Adjustments Testpoints and Indicators 4 Delay Adjustments 5 48 KHz Input Signal Example 5 Specifications 6 Service 7 Functional Description 8 Receive Circuit 8 FPGA 8 FIFO Circuits 9 Line Drivers 9 Frequency Lock LEDs 9 Index ...

Страница 4: ...iv 8914 Instruction Manual Contents ...

Страница 5: ...cribes the features of a specific module of the 8900 Series Distribution Amplifier family As part of this module family it is subject to Safety and Regulatory Compliance described in the 8900 Series frame and power supply documentation see the 8900 Series User s Guide ...

Страница 6: ...vi 8914 Instruction Manual Preface ...

Страница 7: ... passively looped to the second channel to produce seven outputs The 8914 is also a full featured reclocking distribution amplifier that fits inthe 8900 series frame A clock referenced to the applied input reclocks all outputs in each section The delay is set using 16 position rotary switches on the front of the module There are fine and coarse rotary adjustment switches for each delay channel The...

Страница 8: ...er module This module provides the interface for the forced air cover as well as the SMPTE 269M fault reporting health alarm and the error detection For additional information concerning the Controller module refer to the Controller manual Figure 1 8900 Series Frame To install a module into the frame follow these steps 1 Insert the module into the frame connector end first with component side of t...

Страница 9: ...input source to one of the loopthrough input connectors J9 or J10 See Figure 3 Terminate the unused connector into 75Ω Use J7 for input to delay channel 2 J7 is inter nally terminated into 75Ω Figure 3 Typical Module Input and Outputs J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 IN DA1 J2 J4 J6 J8 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 IN DA3 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 IN DA5 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 IN DA2 J...

Страница 10: ...le see Figure 4 Between the testpoints is a green Power On LED Each reclocking section is phase locked to its AES input signal The Lock LEDs on the front of the module are on when the reclocking chip has locked on the incoming AES data stream There is one Lock LED for each channel as shown Figure 4 8914 Adjustments Testpoints and Indicators 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C...

Страница 11: ...tches at 0 0 is 1 2 ms Any switch setting above 0 0 masks the inherent delay and starting at 2 ms adds the selected number of delay increments For example setting Coarse to 0 and Fine to 1 produces 2 ms of delay Each additional Fine switch increment adds 2 ms Setting Coarse to 1 and Fine to 0 produces 32 ms of delay Each additional Coarse switch increment adds 32 ms Table 1 Delay Adjustment Settin...

Страница 12: ...utputs Number Seven 4 delay channel one 3 delay channel two Signal type AES EBU digital audio per AES3id 1995 and SMPTE 276M Connector 75Ω BNC Return loss 25 dB 0 1 to 6 MHz Intrinsic Jitter 6 ns Performance Minimum Output Delay 1 2 ms Maximum Output Delay 510 ms 127 5 AES EBU blocks Environmental Operating temperature range 0 to 45 C noncondensing Non operating temperature range 10 to 70 C noncon...

Страница 13: ...nput signals Verify that source equipment is operating correctly Check cable connections Check output connections for correct I O mapping correct input is used for the corresponding channel output Refer to Figure 4 for supply voltage test points on the 8914 module If the module is still not operating correctly replace it with a known good spare and return the faulty module to a designated Grass Va...

Страница 14: ...ver recovers audio data and low jitter clocks from the digital audio input transmission line The data is reclocked and then sent to the FPGA A special mode allows the preamble and bi phase mark data to pass through in its entirety The 6 144 MHz clock signal is also sent to the FPGA FPGA The FPGAis a field programmable gate array containing proprietary Grass Valley control circuitry The FPGA conver...

Страница 15: ...hes Depending on input signal rate the Fine switch delays the data by 2 to 3 ms increments The Coarse switch delays the data by 30 to 48 ms increments There is a minimum circuit delay of from 1 2 to 1 799 ms for precise adjust ment details see Adjustments Testpoints and Indicators on page 4 FIFO Circuits The FIFO circuits create the signal delay The FIFO receives parallel data from the FPGA All cl...

Страница 16: ...10 8914 Instruction Manual 8914 Dual AES EBU Delay Distribution Amplifier ...

Страница 17: ...ironmental specifications 6 F frame 2 3 6 G ground 4 I impedance 4 indicator 4 input 3 6 loopthrough 3 specification 6 L LEDs 4 lock 4 M module controller 2 installation 2 power supply 2 O outputs 6 connectors 4 specification 6 termination 3 4 P performance 6 phase lock 5 power requirements 6 power supply 2 R repair depot 7 rotary switch 1 4 S specifications 6 switch 4 delay 1 rotary 1 ...

Страница 18: ...Index 2 8914 Instruction Manual T termination 3 testpoints 4 7 troubleshooting 7 ...

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