6 Configuration Mode Introduction
6.2 JTAG Configuration
UG290-2.5.2E
38(98)
Figure 6-16 Process of Background Programming
Start
Verify ID
Code
Erase Flash
Program Flash
Stop
If need to read back to verify data,
Please use
Readable-pattern
at the 1
st
Y-page of the 1
st
X-page.
Erase Internal Flash
For the embedded Flash memory of GW1N series, the embedded
Flash needs to be erased before each programming task. For data security,
the embedded Flash must be erased entirely.
The requirements for JTAG programming frequency are different
according to the different processes of the GW1N series of the embedded
Flash. Please refer to Table 6-8.
Table 6-8 TCK Frequency Requirements for JTAG
Device
TCK Frequency Range Process Code
GW1N-1
GW1N-1S
1.4MHz ~ 5MHz
H
GW1N(RF)-4B
GW1N(SER)-4C
GW1N(R)-9(C)
GW1NZ-1
1MHz ~ 5MHz
T
GW1NS(E)-2(C)
1MHz ~ 5MHz
S
FPGA erasure process of T Technology
The following describes the erase flow of T Technology for GW1NZ-1
in detail, as shown in Figure 6-17.
1.
Establish a JTAG link and reset the TAP;
2.
Read the device ID CODE and check if it matches.
3.
Erase SRAM first if it has been configured.
4.
Send the "0x15" instruction of ConfigEnable;
Содержание GW2AR Series
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