5 Configuration Mode Introduction
5.2 JTAG Configuration
UG290-2.3E
23(87)
5.2.4
JTAG Configuration Process
TAP State Machine
The state machine for the test access port is designed to select an
instruction register or a data register to connect it between TDI and TDO. In
general, the instruction register is used to select the data register to be
scanned. In the state machine diagram, the number on the side of the
arrow indicates the logic state of the TMS when the TCK goes high, as
shown in Figure 5-7.
Figure 5-7 TAP State Machine
TAP Reset
After TMS keeps high (logic "1") and at least 5 strobes are input
(higher and then low) at the TCK terminal, the TAP logic is reset, the TAP
state machine in other states is converted into the state of test logic reset,
and the JTAG port and the test logic are reset.
Note!
The CPU and peripherals are not reset in this state.
Note!
The data on the TDO is valid from the falling edge of TCK in the Shift_DR or Shift_IR
state;
The data is not shifted in the Shift_DR or Shift_IR state;
The data is shifted when leaving the Shift_DR or Shift_IR;
The first to be shifted is the least significant bit (LSB) of the data;
Once reset, all instructions will be reset or disabled.
Instruction Register and Data register
In addition to the test logic reset, the state machine can also control
two basic operations:
