5 Configuration Mode Introduction
5.2 JTAG Configuration
UG290-2.3E
19(87)
Figure 5-3 Trigger Timing
Timing parameters of the LittleBee
®
Family of FPGA Products is as
shown in Table 5-1 .
Table 5-1 Timing Parameters for Cycling Power and RECONFIG_N Trigger
Name
Description
Min.
Max.
T
portready
1
Time from application of V
CC
, V
CCX
and V
CCO
to the
rising edge of READY
50μs
200μs
T
recfglw
RECONFIG_N low pulse width
25ns
-
T
recfgtrdyn
Time from RECONFIG_N falling edge to READY
low
-
70ns
T
readylw
READY low pulse width
TBD
-
T
recfgtdonel
Time from RECONFIG_N falling edge to READY
low
-
80ns
Note!
In the case of MODE0=0, the device power-
up waiting time is 200 μs; If MODE0=1, the
device power-
up waiting time is 50 μs.
Timing parameters of the Arora Family of FPGA Products are as
shown in Table 5-2.
Table 5-2 Timing Parameters for Power-on again and RECONFIG_N Triggering
(Arora Family)
Name
Description
Min.
Max.
T
portready
Time from application of V
CC
, V
CCX
and V
CCO
to the
rising edge of READY
-
23ms
T
recfglw
RECONFIG_N low pulse width
25ns
-
T
recfgtrdyn
Time from RECONFIG_N falling edge to READY
low
-
70ns
T
readylw
READY low pulse width
TBD
-
T
recfgtdonel
Time from RECONFIG_N falling edge to READY
low
-
80ns
5.2
JTAG Configuration
The JTAG configuration mode of Gowin FPGA products conforms to
the IEEE1532 standard and the IEEE1149.1 boundary scan standard.
The JTAG configuration mode writes bitstream data to the SRAM of
Gowin FPGA products. All configuration data is lost after the device is
powered down. All Gowin FPGA products support the JTAG configuration