2 Overview
2.6 Introduction to the I/O BANK
UG823-1.7.2E
9(28)
Pin Name
I/O
Description
DP
NA
USB data pin Data+
REXT
NA
12.7K high-accuracy resistance
XIN
NA
Crystal input signals
XOUT
NA
Crystal oscillator signals
IDPAD
NA
ID signal
VBUSPAD
NA
VBUS signal
VDDA
NA
Analog power supply voltage, VDDA=3.3V
VDDAUSB
NA
Analog power supply pin (3.3V)
VDDDUSB
NA
Analog power supply pin (3.3V)
VDDPL
NA
Power supply pin for driver (1.2V)
Note
!
[1]When the input is single-ended, the GLKC_[x] pin is not a global clock pin.
2.6
Introduction to the I/O BANK
There are four I/O Banks in the GW1NS series of FPGA products,
as shown in Figure 2-1.
Figure 2-1 GW1NS I/O Bank Distribution
GW1NS
I/O BANK0
I/O BANK2
I/O
B
A
N
K
1
I/O
B
A
N
K
3
This manual provides an overview of the distribution view of the
pins in the GW1NS series of FPGA products. The four I/O Banks of the
GW1NS series of FPGA products are marked with four different colors.
User I/O, power, and ground are also marked with different symbols
and colors. The various symbols and colors used for the various pins are
defined as follows:
“
” denotes I/Os in BANK0.
”
” denotes I/Os in BANK1.
”
” denotes I/Os in BANK2.
”
” denotes I/Os in BANK3.
”
” denotes VCC, VCCX, and VCCO.
Содержание GW1NS Series
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