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2 Overview

2.5 Pin Definitions

UG823-1.7.2E

7(28)

2.5

Pin Definitions

The location of the pins in the GW1NS series of FPGA products

varies according to the different packages.

Table 2-5 provides a detailed overview of user I/O, multi-function

pins, dedicated pins, and other pins.

Table 2-5 Definition of the Pins in the GW1NS series of FPGA products

Pin Name

I/O

Description

User I/O Pins

IO[End][Row/Column
Number][A/B]

I/O

[End] indicates the pin location, including L(left)
R(right) B(bottom), and T(top)
[Row/Column Number] indicates the pin
Row/Column number.If [End] is T(top) or
B(bottom), the pin indicates the column number of
the corresponding CFU. If [End] is L(left) or
R(right), the pin indicates the Row number of the
corresponding CFU.
[A/B] indicates differential signal pair information.

Multi-Function Pins

IO[End][Row/Column Number][A/B]/MMM

/MMM represents one or more of the other
functions in addition to being general purpose user
I/O. These pins can be used as user I/O when the
functions are not used.

RECONFIG_N

I, internal weak
pull-up

Start new GowinCONFIG mode when low pulse

READY

I/O

When high level, the device can be programmed
and configured
When low level, the device cannot be programmed
and configured

DONE

I/O

High level indicates successful program and
configure
Low level indicates incomplete or failed to program
and configure

FASTRD_N /D3

I/O

In MSPI mode, FASTRD_N is used as Flash
access speed port. Low indicates high-speed Flash
access mode; high indicates regular Flash access
mode.
Data port D3 in CPU mode

MCLK /D4

I/O

Clock output MCLK in MSPI mode

Data port D4 in CPU mode

MCS_N /D5

I/O

Enable signal MCS_N in MSPI mode, active-low
Data port D5 in CPU mode

MI /D7

I/O

MISO in MSPI mode: Master data input/Slave data
output
Data port D7 in CPU mode

MO /D6

I/O

MISO in MSPI mode: Master data output/Slave
data input
Data port D6 in CPU mode

SSPI_CS_N/D0

I/O

Enable signal SSPI_CS_N in SSPI mod,
active-low, Internal Weak Pull Up
Data port D0 in CPU mode

SO /D1

I/O

MISO in MSPI mode: Master data input/Slave data
output

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Содержание GW1NS Series

Страница 1: ...GW1NS series of FPGA Products Package Pinout User Guide UG823 1 7 2E 06 30 2021 ...

Страница 2: ... mechanical photocopying recording or otherwise without the prior written consent of GOWINSEMI Disclaimer GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions ...

Страница 3: ...019 1 3E CS36 package outline updated 10 12 2019 1 4E GW1NS 4 GW1NS 4C added 11 12 2019 1 5E CS49 package info added and CS49 POD added 03 30 2020 1 6E GW1NS 2 GW1NS 2C CS36U package info added 04 16 2020 1 6 1E GW1NS 2C CS36U package info removed The pins distribution view and pin number of GW1NS 4 GW1NS 4C QN48 updated 07 28 2020 1 7E GW1NS 4 4C MG64 package info Added 11 25 2020 1 7 1E CS49 pac...

Страница 4: ...of GW1NS 4 GW1NS 4C Pins 6 2 5 Pin Definitions 7 2 6 Introduction to the I O BANK 9 3 View of Pin Distribution 11 3 1 View of GW1NS 2 GW1NS 2C Pins Distribution 11 3 1 1 View of QN32 Pins Distribution 11 3 1 2 View of QN32U Pins Distribution 12 3 1 3 View of CS36 Pins Distribution 13 3 1 4 View of CS36U Pins Distribution 14 3 1 5 View of QN48 Pins Distribution 15 3 1 6 View of LQ144Pins Distributi...

Страница 5: ... 21 4 3 CS36 Package Outline 2 5mm x 2 5mm 22 4 4 CS36U Package Outline 2 5mm x 2 5mm 23 4 5 CS49 Package Outline 2 9mm x 2 9mm 24 4 6 QN48Package Outline GW1NS 2 GW1NS 2C 6mm x 6mm 25 4 7 QN48Package Outline GW1NS 4 GW1NS 4C 6msm x 6mm 26 4 8 LQ144 Package Outline 22mm x 22mm 27 4 9 MG64 Package Outline 4 2mm x 4 2mm 28 ...

Страница 6: ... Figure 3 6 View of GW1NS 2 GW1NS 2C LQ144 Pins Distribution Top View 16 Figure 3 7 View of GW1NS 4 GW1NS 4C CS49 Pins Distribution Top View 17 Figure 3 8 View of GW1NS 4 GW1NS 4C QN48 Pins Distribution Top View 18 Figure 3 9 View of GW1NS 4 GW1NS 4C MG64 Pins Distribution Top View 19 Figure 4 1 Package Outline QN32 20 Figure 4 2 Package Outline QN32U 21 Figure 4 3 Package Outline CS36 22 Figure 4...

Страница 7: ...the Pins in the GW1NS series of FPGA products 7 Table 3 1 Other Pins in GW1NS 2 GW1NS 2C QN32 11 Table 3 2 Other pins in GW1NS 2 GW1NS 2C QN32U 12 Table 3 3 Other pins in GW1NS 2 GW1NS 2C CS36 13 Table 3 4 Other pins in GW1NS 2 CS36U 14 Table 3 5 Other pins in GW1NS 2 GW1NS 2C QN48 15 Table 3 6 Other pins in GW1NS 2 GW1NS 2C LQ144 16 Table 3 7 Other pins in GW1NS 4 GW1NS 4C CS49 17 Table 3 8 Other...

Страница 8: ...ibution of pins and package diagrams 1 2 Related Documents The latest user guides are available on GOWINSEMI Website You can find the related documents at www gowinsemi com 1 DS821 GW1NS series of FPGA Products Data Sheet 2 UG290 Gowin FPGA Products Programming and Configuration User Guide 3 UG823 GW1NS series of FPGA Products Package and Pinout 4 UG822 GW1NS 2 Pinout 5 UG825 GW1NS 2C Pinout 6 UG8...

Страница 9: ...rammable Gate Array GPIO Gowin Programmable IO QN32 QFN32 package QN32U QFN32U package CS36 WLCSP36 package CS36U WLCSP36U package CS49 WLCSP49 package QN48 QFN48 Package LQ144 LQFP144 package MG64 MBGA64 1 4 Support and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly usin...

Страница 10: ...tions which provide excellent calculation functions and exceptional system response interrupts They also offer high performance low power consumption a small number of pins flexible usage instant start up affordability nonvolatile high security and abundant package types among other benefits The GW1NS series of SoC FPFA products achieve seamless connection between programmable logic devices and em...

Страница 11: ... x 2 9 42 8 MG64 0 5 4 2 x 4 2 57 8 LQ144 0 5 20 x 20 95 12 95 12 Note In this manual abbreviations are employed to refer to the package types See 1 3 Abbreviations and Terminology The JTAGSEL_N and JTAG pins cannot be used as I O simultaneously The data in this table is when the loaded four JTAG pins TCK TDI TDO and TMS are used as I O When mode 2 0 001 JTAGSEL_N and the four JTAG pins TCK TDI TD...

Страница 12: ...0 22 38 95 Differential Pair 10 5 14 10 16 44 True LVDS Output 4 2 6 5 7 12 VCCO0 1 0 0 0 0 0 VCCO1 0 0 0 0 1 1 VCCO2 1 1 1 1 1 2 VCCO3 0 1 0 1 0 2 VCC VCCPLL 3 2 0 1 0 2 0 VCCO1 VCCO3 VCCP VCCX 2 0 0 0 0 0 VCCO1 VCCX VDDAUSB VDDDU SB 0 0 0 1 0 0 VBUSPAD VCCO1 VCCX VDDAU SB VDDDUSB 0 2 0 0 0 0 VCC VCCPLL VDDPL 0 3 0 1 0 4 VCCO0 VDDA 0 2 1 1 0 3 VCCO1 VCCO3 0 0 1 0 0 0 VCCP VCCX 0 0 1 0 2 0 VCCO0 V...

Страница 13: ...ANK0 8 3 0 8 3 0 9 3 0 BANK1 18 9 0 10 5 0 28 14 0 BANK2 16 8 8 9 4 4 18 9 9 BANK3 0 0 0 11 5 0 0 0 0 Max User I O 2 42 38 56 Differential Pair 20 17 26 True LVDS output 8 4 9 VCC 1 2 1 VCCX 1 1 1 VCCO0 0 1 1 VCCO1 1 1 1 VCCO2 1 1 1 VCCO3 0 2 1 VCCO0 VCCO33 1 0 0 VSS 2 1 2 MODE0 0 0 0 MODE1 0 1 0 MODE2 0 0 0 JTAGSEL_N 0 1 1 NC 0 0 0 Note 1 Single end Differential I O quantity include CLK pins and ...

Страница 14: ...purpose user I O These pins can be used as user I O when the functions are not used RECONFIG_N I internal weak pull up Start new GowinCONFIG mode when low pulse READY I O When high level the device can be programmed and configured When low level the device cannot be programmed and configured DONE I O High level indicates successful program and configure Low level indicates incomplete or failed to ...

Страница 15: ...nput output of D 7 0 in CPU mode GCLKT_ x I Pins in global clock input T True x global clock No GCLKC_ x I Differential comparison input pin of GCLKT_ x C Comp x global clock No 1 LPLL_T_fb RPLL_T_fb I L R PLL feedback input pin T True LPLL_C_fb RPLL_C_fb I L R PLL feedback input pin C Comp LPLL_T_in RPLL_T_in I L R PLL clock input pin T True LPLL_C_in RPLL_C_in I L R PLL clock input pin C Comp MO...

Страница 16: ...lobal clock pin 2 6 Introduction to the I O BANK There are four I O Banks in the GW1NS series of FPGA products as shown in Figure 2 1 Figure 2 1 GW1NS I O Bank Distribution GW1NS I O BANK0 I O BANK2 I O BANK1 I O BANK3 This manual provides an overview of the distribution view of the pins in the GW1NS series of FPGA products The four I O Banks of the GW1NS series of FPGA products are marked with fo...

Страница 17: ...2 Overview 2 6 Introduction to the I O BANK UG823 1 7 2E 10 28 denotes VCC The filling color does not change denotes VSS The filling color does not change denotes NC ...

Страница 18: ... 3 View of Pin Distribution 3 1 View of GW1NS 2 GW1NS 2C Pins Distribution 3 1 1 View of QN32 Pins Distribution Figure 3 1 View of GW1NS 2 GW1NS 2C QN32 Pins Distribution Top View Table 3 1 Other Pins in GW1NS 2 GW1NS 2C QN32 VCCO0 19 VCCO2 6 VCC VCCPLL 2 18 VCCO1 VCCO3 VCC P VCCX 15 31 VSS 3 ...

Страница 19: ...UG823 1 7 2E 12 28 3 1 2 View of QN32U Pins Distribution Figure 3 2 View of GW1NS 2 GW1NS 2C QN32 Pins Distribution Top View Table 3 2 Other pins in GW1NS 2 GW1NS 2C QN32U VCCO0 VDDA 19 23 VCCO2 6 VCCO3 31 VCC VDDPL VCCPLL 2 18 7 VBUSPAD VCCO1 VCCX VDDAUSB VDDDUSB 11 15 VSS 3 ...

Страница 20: ...Pins Distribution UG823 1 7 2E 13 28 3 1 3 View of CS36 Pins Distribution Figure 3 3 View of GW1NS 2 GW1NS 2C CS36 Pin Distribution Top View Table 3 3 Other pins in GW1NS 2 GW1NS 2C CS36 VCCO1 VCCO3 C4 VCCO2 F1 VCCX VCCP D3 VCC VCCPLL D4 VSS C3 VDDA VCCO0 A6 ...

Страница 21: ...istribution UG823 1 7 2E 14 28 3 1 4 View of CS36U Pins Distribution GW1NS 2 Figure 3 4 View of GW1NS 2 CS36U Pins Distribution Top View Table 3 4 Other pins in GW1NS 2 CS36U VCCO2 F1 VCCO3 D3 VCCX VCCO1 VDDAUSB VDDDUSB C4 VCC VCCPLL VDDPL D4 VSS AGND C3 VCCO0 A6 ...

Страница 22: ... Distribution UG823 1 7 2E 15 28 3 1 5 View of QN48 Pins Distribution Figure 3 5 View of GW1NS 2 GW1NS 2C QN48 Pins Distribution Top View Table 3 5 Other pins in GW1NS 2 GW1NS 2C QN48 VCCO1 25 VCCO2 13 VCCX VCCP 8 36 VCC VCCPLL 12 37 VDDA VCCO0 VCCO3 1 VSS 2 26 ...

Страница 23: ...n Figure 3 6 View of GW1NS 2 GW1NS 2C LQ144 Pins Distribution Top View Table 3 6 Other pins in GW1NS 2 GW1NS 2C LQ144 VDDA VCCO0 109 127 144 VCCO1 91 VCCO2 37 55 VCCO3 5 26 VCCX VDDAUSB 31 103 78 VCC VDDPL VCCPLL 1 36 73 108 VBUSPAD 82 VDDDUSB 85 VSS 2 17 33 35 53 74 89 105 107 125 NC 6 10 19 32 34 48 49 50 51 52 56 57 92 93 94 ...

Страница 24: ... UG823 1 7 2E 17 28 3 2 View of GW1NS 4 GW1NS 4C Pins Distribution 3 2 1 View of CS49 Pins Distribution Figure 3 7 View of GW1NS 4 GW1NS 4C CS49 Pins Distribution Top View Table 3 7 Other pins in GW1NS 4 GW1NS 4C CS49 VCC D5 VCCO1 C3 VCCO2 E3 VCCX D3 VCCO0 VCCO3 C5 VSS D4 C4 ...

Страница 25: ... 4C Pins Distribution UG823 1 7 2E 18 28 3 2 2 View of QN48 Pins Distribution Figure 3 8 View of GW1NS 4 GW1NS 4C QN48 Pins Distribution Top View Table 3 8 Other pins in GW1NS 4 GW1NS 4C QN48 VCC 11 37 VCCO0 5 VCCO1 38 VCCO2 36 VCCO3 12 24 VCCX 25 VSS 26 ...

Страница 26: ...S 4C Pins Distribution UG823 1 7 2E 19 28 3 2 3 View of MG64 Pins Distribution Figure 3 9 View of GW1NS 4 GW1NS 4C MG64 Pins Distribution Top View Table 3 9 Other pins in GW1NS 4 GW1NS 4C MG64 VCC D5 VCCO0 C3 VCCO1 C6 VCCO2 F6 VCCO3 F3 VCCX E4 VSS D4 E5 ...

Страница 27: ...4 Package Diagrams 4 1 QN32 Package Outline 5mm x 5mm UG823 1 7 2E 20 28 4 Package Diagrams 4 1 QN32 Package Outline 5mm x 5mm Figure 4 1 Package Outline QN32 ...

Страница 28: ...4 Package Diagrams 4 2 QN32U Package Outline 5mm x 5mm UG823 1 7 2E 21 28 4 2 QN32U Package Outline 5mm x 5mm Figure 4 2 Package Outline QN32U ...

Страница 29: ...4 Package Diagrams 4 3 CS36 Package Outline 2 5mm x 2 5mm UG823 1 7 2E 22 28 4 3 CS36 Package Outline 2 5mm x 2 5mm Figure 4 3 Package Outline CS36 ...

Страница 30: ...4 Package Diagrams 4 4 CS36U Package Outline 2 5mm x 2 5mm UG823 1 7 2E 23 28 4 4 CS36U Package Outline 2 5mm x 2 5mm Figure 4 4 Package Outline CS36U ...

Страница 31: ...4 Package Diagrams 4 5 CS49 Package Outline 2 9mm x 2 9mm UG823 1 7 2E 24 28 4 5 CS49 Package Outline 2 9mm x 2 9mm Figure 4 5 Package Outline CS49 ...

Страница 32: ...igure 4 6 Package Outline QN48 GW1NS 2 GW1NS 2C PAD ZONE EXPOSED THERMAL BOTTOM VIEW 4 20 4 20 4 10 4 30 4 10 4 30 2 2 1 177 177 L F载体尺寸 MIL Ne 4 40BSC c 0 20 0 15 0 25 0 A1 0 05 0 02 0 75 6 00 6 10 e 0 40BSC E2 0 70 0 80 E D2 A D 0 23 0 18 0 20 b MAX NOM MIN MILLIMETER SYMBOL 5 90 6 10 6 00 5 90 L 0 45 0 35 0 40 0 30 0 40 h 0 35 4 40BSC Nd ...

Страница 33: ...mm Figure 4 7 Package Outline QN48 GW1NS 4 GW1NS 4C PAD ZONE EXPOSED THERMAL BOTTOMVIEW 4 20 4 20 4 10 4 30 4 10 4 30 177 177 L F载体尺寸 MIL Ne 4 40BSC c 0 20 0 15 0 25 __ A1 0 05 0 02 0 85 6 00 6 10 e 0 40BSC E2 0 75 0 85 E D2 A D 0 23 0 18 0 20 b MAX NOM MIN MILLIMETER SYMBOL 5 90 6 10 6 00 5 90 L 0 45 0 35 0 40 0 30 0 40 h 0 35 4 40BSC Nd ...

Страница 34: ...4 Package Diagrams 4 8 LQ144 Package Outline 22mm x 22mm UG823 1 7 2E 27 28 4 8 LQ144 Package Outline 22mm x 22mm Figure 4 8 LQ144 Package Outline ...

Страница 35: ...Diagrams 4 9 MG64 Package Outline 4 2mm x 4 2mm UG823 1 7 2E 28 28 4 9 MG64 Package Outline 4 2mm x 4 2mm Figure 4 9 MG64 Package Outline A 1 2 3 4 B C D 5 6 7 8 E F G H A 1 2 3 4 B C D 5 6 7 8 E F G H A 1 2 B C ...

Страница 36: ......

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