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2 Overview
2.5 Pin Definitions
UG119-1.5E
8(34)
2.4.4
Quantity of GW1NR-9 Pins
Table 2-7 Quantity of GW1NR-9 Pins
Pin Type
GW1NR-9
QN88
QN88P
LQ144
P
MG100
P
MG100
PF
MG100
PA
MG100
PT
MG100
PS
I/O Single
end/Differ
ential
pair/LVD
S
[1]
BANK0
0/0/0
0/0/0
18/9/0
12/6/0
12/6/0
12/6/0
12/6/0
12/6/0
BANK1 25/11/4
25/11/4
32/12/4
22/5/1
22/6/1
22/6/1
22/5/1
22/6/1
BANK2
23/11/1
1
23/11/1
1
40/19/1
4
32/15/1
4
32/15/1
4
32/15/1
4
32/15/1
4
32/15/1
4
BANK3
22/8/4
22/6/3
30/8/2
21/4/1
21/6/1
21/6/2
21/4/2
21/6/2
Max. User I/O
[2]
70
70
120
87
87
87
87
87
Differential Pair
30
28
48
30
33
33
30
33
True LVDS output
19
18
20
16
16
17
17
17
VCC
4
4
4
3
3
3
3
3
VCCX
0
0
2
1
1
1
1
1
VCCO0
0
0
2
1
1
1
1
1
VCCO1
1
1
2
1
1
1
1
1
VCCO2
2
2
2
1
1
1
1
1
VCCO3
1
1
2
1
1
1
1
1
VCCX/VCCO0
[3]
3
3
0
0
0
0
0
0
VSS
6
6
9
4
4
4
4
4
MODE0
1
1
1
0
0
0
0
0
MODE1
1
1
1
1
1
1
1
1
MODE2
0
0
0
0
0
0
0
0
JTAGSEL_N
1
1
1
1
1
1
1
1
Note!
[1]Quantity of single end/ differential/LVDS I/O include CLK pins, and download
pins;
[2]The JTAGSEL_N and JTAG pins cannot be used as I/O simultaneously. The
data in this table is when the loaded four JTAG pins (TCK, TDI, TDO, and TMS)
are used as I/O.
[3]Pin multiplexing.
2.5
Pin Definitions
The location of the pins in the GW1NR series of FPGA products
varies according to the different packages.
Table 2-8 provides a detailed overview of user I/O, multi-function
pins, dedicated pins, and other pins.
Содержание GW1NR Series
Страница 1: ...GW1NR series of FPGA products Package Pinout User Guide UG119 1 5E 02 02 2021 ...
Страница 35: ...4 Package Diagrams UG119 1 5E 28 34 4Package Diagrams ...
Страница 42: ......