User Manual
MIFARE SAM AV3 Evaluation Board
User manual COMPANY PUBLIC
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© GMMC GmbH. 2020. All rights reserved.
Rev. 1.0 19-JAN-2022
9
SPI
For SPI communication between MCU and CLRC663 the 4 jumpers on the 10 pin header need to be
positioned as shown. This setting is intended to use the MIFARE SAM AV3 in S-mode, or in an S/X
mixed mode. At this point, the MCU can already control the CLRC663 via SPI.
6.1.1
I²C
In case I²C is selected, the CLRC663 will be controlled by the MIFARE SAM AV3 in X- mode. The 4
jumpers need to be inserted in the 10 pin header as shown, these correspond to the ADR0 and ADR1 pins
on the CLRC663 host interface in I²C configuration.
Now the host interface of the CLRC663 is configured as I²C and both ADR pins are pulled to low. The
MIFARE SAM AV3 Master I²C interface (SAM_I²C_xxx) can be routed to the host interface of the
CLRC663. This is done with JP1 and JP2.
6.1.2
CLRC663 SAM I²C Interface
The CLRC663 SAM interface is a dedicated second interface for MIFARE SAM X-mode operation. As this
interface is switched off per default, the I²C signal from the MIFARE SAM AV3 needs to be set routed to
interface 2 on JP1 and JP2.
If this interface is already activated by setting the corresponding bits in the HostCtl register of the
CLRC663, the above setting is sufficient to communicate between CLRC663 and the MIFARE SAM AV3.
If not, then an additional SPI connection for the MCU to the CLRC663 is needed, to activate the SAM
interface.
Figure 14: Jumper settings SPI or I²C Host interface mode
Figure 15: Selection of CLRC663 SAM interface
