Global American 3304220, Руководство пользователя

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2.10 System Memory DRAM
The 3304220 provides a wide range on-board DRAM memory sizes from 1 MB to 16
MB by using 1, 2, 4, 8 or 16MB 72-pin SIMMs (Single In-Line Memory Modules)
with access time should be 70 n-second or faster.
The 3304220 provides two banks for memory installation by SIMM RAM module
on card. The banks are designated as Bank0 and Bank1. See the figure on section 2.3
for get the identifying the banks. You must use from Bank0 first if install one SIMM
only. If you are using both banks, the memory capacity of both SIMMs should be the
same.
2.11 Watch-Dog Timer
There are three access cycles of Watch-Dog Timer as Enable, Refresh and Disable. The
Enable cycle should proceed by READ PORT 443H. The Disable cycle should
proceed by READ PORT 043H. A continue Enable cycle after a first Enable cycle
means Refresh.
Once if the Enable cycle activity, a Refresh cycle is request before the time-out period
for restart counting the WDT Timer's period. Otherwise, it will assume that the
program operation is abnormal when the time counting over the period preset of
WDT Timer. A System Reset signal to start again or a NMI cycle to the CPU comes if
over.
The JP21 is using for select the active function of watch -dog timer in disable the
watch-dog timer, or presetting the watch -dog timer activity at the reset trigger, or
presetting the watch -dog timer activity at the NMI trigger.
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JP21 : Watch-Dog Active Type Setting
JP21 DESCRIPTION
*1-2 System Reset
2-3 Active NMI
OFF disable Watch-dog timer