5.2
Port A and Switch Register
The low six bits of the onboard Port A parallel I/O port (
0x0000
) are mapped to the upper six
positions of switch pack
SW1
. These bits are active high (a closed switch position reads as a binary
1). The upper two bits of Port C are used for the onboard UART and are not available as parallel
I/O pins. The bits of Port A are mapped as follows:
Port A Bit
Function
Notes
0
PA0, SW2-8
ROMFS record, bit 0, closed reads 1
1
PA1, SW2-7
ROMFS record, bit 1, closed reads 1
2
PA2, SW2-6
ROMFS record, bit 2, closed reads 1
3
PA3, SW2-5
ROMFS record, bit 3, closed reads 1
4
PA4, SW2-4
Bitrate selection, closed reads 1
5
PA5, SW2-3
Bitrate selection, closed reads 1
6
UART Transmit Data
7
UART Receive Data
Bits 0 through 5 reflect the state of SW2 positions 8 through 3. A 1 in a given bit position corresponds
to a closed switch. These positions are labeled
PA0 - PA5
in the silkscreen.
PA0 - PA3
can be used
by Glitch Works software to select the ROMFS record to load into memory at reset.
PA4 - PA5
are used by Glitch Works software to set the console UART bitrate, as described in Section 2.1,
“Configuring Console Speed.”
Bits 6 and 7 are used by the R65X1Q internal UART and are not available as parallel I/O pins.
5.3
Memory Map
The R65X1Q SBC operates in “Full Address Mode” and has the following memory map:
Address Range
Contents
0x0000 - 0x0003
Parallel I/O ports
0x0004 - 0x000F
Reserved (not usable)
0x0010 - 0x001F
R65X1Q control registers
0x0020 - 0x003F
Reserved (not usable)
0x0040 - 0x00FF
R65X1Q internal RAM
0x0100 - 0x7FFF
Static RAM, IC socket U3
0x8000 - 0xEEFF
Glitchbus expansion memory space
0xEF00 - 0xEFFF
Glitchbus expansion I/O space
0xFF00 - 0xFFFF
Glitchbus expansion memory space, when ROM is disabled
0xFF00 - 0xFFFF
4K page of ROM, IC socket U2, when ROM is enabled
Memory occupied by the static RAM in socket U2 may be overlaid by external devices on the
Glitchbus using the
*BMASK
signal.
Consult the Rockwell R6500 family datasheet specific to the processor in use for more information
about onboard I/O and memory devices.
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