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5.2

Port A and Switch Register

The low six bits of the onboard Port A parallel I/O port (

0x0000

) are mapped to the upper six

positions of switch pack

SW1

. These bits are active high (a closed switch position reads as a binary

1). The upper two bits of Port C are used for the onboard UART and are not available as parallel
I/O pins. The bits of Port A are mapped as follows:

Port A Bit

Function

Notes

0

PA0, SW2-8

ROMFS record, bit 0, closed reads 1

1

PA1, SW2-7

ROMFS record, bit 1, closed reads 1

2

PA2, SW2-6

ROMFS record, bit 2, closed reads 1

3

PA3, SW2-5

ROMFS record, bit 3, closed reads 1

4

PA4, SW2-4

Bitrate selection, closed reads 1

5

PA5, SW2-3

Bitrate selection, closed reads 1

6

UART Transmit Data

7

UART Receive Data

Bits 0 through 5 reflect the state of SW2 positions 8 through 3. A 1 in a given bit position corresponds
to a closed switch. These positions are labeled

PA0 - PA5

in the silkscreen.

PA0 - PA3

can be used

by Glitch Works software to select the ROMFS record to load into memory at reset.

PA4 - PA5

are used by Glitch Works software to set the console UART bitrate, as described in Section 2.1,
“Configuring Console Speed.”

Bits 6 and 7 are used by the R65X1Q internal UART and are not available as parallel I/O pins.

5.3

Memory Map

The R65X1Q SBC operates in “Full Address Mode” and has the following memory map:

Address Range

Contents

0x0000 - 0x0003

Parallel I/O ports

0x0004 - 0x000F

Reserved (not usable)

0x0010 - 0x001F

R65X1Q control registers

0x0020 - 0x003F

Reserved (not usable)

0x0040 - 0x00FF

R65X1Q internal RAM

0x0100 - 0x7FFF

Static RAM, IC socket U3

0x8000 - 0xEEFF

Glitchbus expansion memory space

0xEF00 - 0xEFFF

Glitchbus expansion I/O space

0xFF00 - 0xFFFF

Glitchbus expansion memory space, when ROM is disabled

0xFF00 - 0xFFFF

4K page of ROM, IC socket U2, when ROM is enabled

Memory occupied by the static RAM in socket U2 may be overlaid by external devices on the
Glitchbus using the

*BMASK

signal.

Consult the Rockwell R6500 family datasheet specific to the processor in use for more information
about onboard I/O and memory devices.

10

Содержание GW-R65X1QSBC-1

Страница 1: ...11Q SBC GW R65X1QSBC 1 User s Manual and Assembly Guide Revision 2 2020 10 03 c 2020 Glitch Works LLC http www glitchwrks com This manual is licensed under a Creative Commons Attribution NonCommercial...

Страница 2: ...6 3 3 Insert Socketed ICs 6 3 4 Assemble Console Cable 7 3 5 Optional Glitchbus Expansion 7 4 Initial Checkout and Testing 8 4 1 Troubleshooting 8 4 2 Repair and Service 8 5 Technical Notes 9 5 1 Por...

Страница 3: ...r the storage of file records in ROM These records can be loaded from the monitor or automatically selected by option switches on reset power up This also allows for in board updates without overwriti...

Страница 4: ...speed is required it is recommended that a 2 MHz system clock be used While Rockwell only specs the A suffix R6501AQ and R6511AQ for 2 MHz operation internal testing has shown good results with runni...

Страница 5: ...e or below the SBC using PC 104 style stacking headers The R65X1Q SBC can also be used with right angle headers and a Glitchbus backplane The Glitchbus includes signals for separate memory and I O add...

Страница 6: ...com adafruit guide excellent soldering 3 1 Assembling the R65X1Q SBC If you purchased a full Glitch Works parts kit we recommend completing all assembly sections since extra features can be disabled a...

Страница 7: ...essors due to the force required for insertion and removal Note that QUIP package processors have a big notch at both ends and a smaller off center notch to indicate pin 1 Install 33 F 35 V capacitor...

Страница 8: ...ins for software control Consult the schematic for more information A serial light box will help debug potential serial wiring problems we highly recommend the addition of a light box to your toolkit...

Страница 9: ...ng If your R65X1Q SBC fails to come up recheck all solder joints for cold joints bridges or missed pins this is by far the most common problem we ve observed during assembly workshops Recheck con figu...

Страница 10: ...lable at 0xF000 These bits are set on reset so that the last page of ROM is available for booting Writing to these bits immediately changes the ROM page Port C provides readback of these bits Bit 3 en...

Страница 11: ...Glitch Works software to select the ROMFS record to load into memory at reset PA4 PA5 are used by Glitch Works software to set the console UART bitrate as described in Section 2 1 Configuring Console...

Страница 12: ...1 ROM Compatibility The ROM socket at U2 is compatible with JEDEC standard 32K x 8 static RAM Ferroelectric RAM FeRAM and 28C256 EEPROMs It may not be compatible with some manufacturers UV EPROMs such...

Страница 13: ...ve 1x 4 MHz crystal 1x Rockwell R6501Q CPU 1x 28C256 EEPROM preloaded with R65X1Q SBC firmware 1x JEDEC 62256 type 32K x 8 static RAM 1x 74LS04 hex inverter 1x 74LS10 triple 3 input NAND gate 1x 74LS2...

Страница 14: ...parts list may be shipped as a 7404 74S04 74F04 74LS04 74ALS04 or 74HCT04 All 4 7 k resistors on the GW R65X1QSBC 1 are pull up or pull down resistors and may be any value from 2 2 k to 10 k even thou...

Страница 15: ......

Страница 16: ...CE 20 A10 21 OE 22 A11 23 A9 24 A8 25 A13 26 WE 27 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 U2 32K ROM A7 A6 A5 A4 A3 A2 A1 A0 RPA0 A11 A10 A9 A8 RPA2 RPA1 D0 D2 D4 D6 D1 D3 D5 D7 C11 22p C10 22p GND GND 1...

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