Glitch Works 8085 SBC, Руководство пользователя и инструкция по сборке

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2.1 Configuring I/O
The addresses of the USART registers, the board status register, and the board control register are
controlled by switch pack SW2. In a default configuration, SW2 is set to all open and places the
I/O base at
0x00 - 0x03
. The base I/O block may be re-addressed on any four-byte boundary in
address space for use with other software.
2.2 ROM Options
ROM configuration on the 8085 SBC rev 3 is flexible. ROM is addressed in 4K pages, using the
ROM base set on SW3 and three bits from the board control register. The board control register is
software programmable, and is reset to
0x00
at reset and power-on.
A pair of D-type flip-flops allows switching the ROM on or off under software control, as well as
mapping ROM to
0x0000
for booting. The default states for these flip-flops are controlled by jumpers
J1 and J2. J1 controls remapping to
0x0000
for booting: place its shunt from 1-2 to disable ROM
boot, or from 2-3 to enable ROM boot. J2 controls whether the ROM is enabled or disabled at reset.
Place its shunt from 1-2 to disable ROM at reset, or from 2-3 to enable ROM at reset.
Note that
ROM must be enabled at reset for ROM boot to work (both J1 and J2 must be strapped for 2-3) .
2.3 Interrupt Jumpering
The five hardware interrupt lines of the Intel 8085 are pulled down to an inactive state with 4.7 kΩ
resistors. While they are not used by the default Glitch Works software package, they are available
for use. Additionally, the
*BINT
line from the Glitchbus expansion header is inverted and brought to
TP1,
INTERRUPT
. It may be jumpered to any of the five available hardware interrupts. Consult the
schematic for further details.
2.4 Glitchbus Expansion
The 8085 SBC rev 3 is expandable through a Glitchbus expansion header. The Glitchbus is a generic
8-bit bus intended to be processor-agnostic. We plan on offering many expansion boards that utilize
this bus design. As implemented on the 8085 SBC rev 3, the Glitchbus is designed to stack above
the SBC using PC/104 style stacking headers.
Do note that some of the status and control lines are not fully buffered on the 8085 SBC rev 3 and
are subject to loading limitations.
The 8085 SBC’s Glitchbus expansion header is not compatible with previous expansion boards designed
for past revisions of the Glitch Works 8085 SBC. Previous boards will not work with the 8085 SBC
rev 3 – use only Glitchbus compatible expansion boards!
Previous boards are of a different physical
size and should be fairly hard to get mixed up with Glitchbus boards.
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