GD32W51x User Manual
749
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MASK [15:0]
rw
Bits
Fields
Descriptions
31:0
MASK[31:0]
Status mask
Mask to be applied to the status bytes received from the flash memory.
For bit n:
0: Bit n of the data received is masked and its value is not considered in the matching
logic
1: Bit n of the data received is unmasked and its value is considered in the matching
logic
This field can be w ritten only w hen BUSY = 0.
22.11.18.
Status match register (QSPI_ STATMATCH)
Address offset: 0x28
Reset value: 0x0000 0000
This register can be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
MATCH [31:16]
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MATCH [15:0]
rw
Bits
Fields
Descriptions
31:0
MATCH[31:0]
Status match
Expected value to be compared w ith the masked status register to get a match.
This field can be w ritten only w hen BUSY = 0.
22.11.19.
Interval register (QSPI_INTERVAL)
Address offset: 0x2C
Reset value: 0x0000 0000
This register can be accessed by word (32-bit).
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Reserved
rw
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INTERVAL [15:0]
rw
Содержание GD32W515 Series
Страница 1: ...GigaDevice Semiconductor Inc GD32W51x Arm Cortex M33 32 bit MCU User Manual Revision 1 0 Nov 2021 ...
Страница 66: ...GD32W51x User Manual 66 Bits Fields Descriptions 31 0 UNIQUE_ID 95 64 Unique device ID ...
Страница 389: ...GD32W51x User Manual 389 The FWDGT timeout can be more accurate by calibrating the IRC32K ...
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