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GD32A50x User Manual
55
When an ECC error is reported, a new read at the error address may not generate an ECC
error if the data is still present in the current buffer / prefetch buffer / cache, even if ECCCOR
and ECCDET are cleared.
2.3.3.
Read operations
The flash can be addressed directly as a common memory space. Any instruction fetch and
the data access from the flash are through the AHB BUS from the CPU.
Wait state added:
The WSCNT bits in the FMC_WS register needs to be configured correctly depend on the
AHB clock frequency when reading the flash memory. The relation between WSCNT and
AHB clock frequency is show as the
Table 2-5. The relation between WSCNT and AHB
clock frequency when LDO is 1.1V
Table 2-5. The relation between WSCNT and AHB clock frequency when LDO is 1.1V
AHB clock frequency
WSCNT configured
<= 25MHz
0 (0 wait state added)
<= 50MHz
1 (1 wait state added)
<= 75MHz
2 (2 wait state added)
<= 100MHz
3 (3 wait state added)
If system reset occurs, the AHB clock frequency is 8MHz and the WSCNT is 0.
Note:
1. If it is necessary to increase the AHB clock frequency, firstly, refer to
relation between WSCNT and AHB clock frequency when LDO is 1.1V
, configure the
WSCNT bits according to the target AHB clock frequency. Then, increase the AHB clock
frequency to the target frequency. It is forbidden to increase the AHB clock frequency before
configuring the WSCNT.
2. If it is necessary to decrease the AHB clock frequency, firstly, decrease the target AHB
clock frequency. Then refer to
Table 2-5. The relation between WSCNT and AHB clock
, configure the WSCNT bits according the target AHB clock
frequency. It is forbidden to configure the WSCNT bits before decrease the AHB clock
frequency.
Considering that the wait state is added, the read efficiency is very low (such as add 3 wait
state when 100MHz). In order to speed up the read access, there are some functions
performed as below.
Current buffer:
The current buffer is always enabled. Each time read from flash memory, 64-bit data will be
get and store in current buffer. The CPU only need 32-bit or 16-bit buffer in each read