Gigabyte 6CX7 Series, Руководство пользователя, Страница: 72 / 108

6CX7 Motherboard
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Introduce RIMM (Rambus In-line Memory Module)
Direct Rambus Memory Controller
⇒
Directly support a
single
Direct Rambus * Channel
Ÿ
Supports 300&400 / 356&400 MHz Direct Rambus * Channel @ 100/133MHz host bus
frequency.
Ÿ
Maximum memory array size up to 256MB using 64Mb/72Mb, 512MB using
128Mb/144Mb, 1GB using 256Mb/288Mb DRAM technology
⇒ Supports up to 32 Direct Rambus devices per channel
⇒ Supports a maximum DRAM address decode space of 4GB
⇒
Configurable optional ECC operation
Ÿ
ECC with single bit Error Correction and multiple bit Error Detection
Ÿ
Single bit errors corrected and written back to memory (auto-scrubbing)
Ÿ
Parity mode not supported
DRAM Interface
The MCH supports a single channel of Direct RDRAM memory using RSL technology. 300 and
400MHz Direct RDRAM devices are supported. 64, 128 and 256Mb technology Direct RDRAM
devices are supported. A maximum of 32 Direct RDRAM devices (64Mb technology = 256MB max)
are supported for a single channel. The following table shows the maximum DRAM array size and the
minimum increment size for the various DRAM densities supported for MCH.
RDRAM Technology Increments Maximum
64Mb/72Mb 8MB 256MB
128Mb/144Mb 16MB 512MB
256Mb/288Mb 32MB 1GB
The MCH provides optional ECC error checking for DRAM data integrity. During DRAM writes ECC
is generated on a QWORD (64bit) basis. Partial QWORD writes require a read-modify-write cycle when
ECC is enabled. During DRAM reads, the MCH supports detection of single-bit and multiple-bit errors,
and will correct single bit errors when correction is enabled. The MCH will automatically scrub single bit
errors by writing the corrected value back into DRAM when scrubbing is enabled. ECC can only be
enabled when the Direct RDRAMs support the extra two data bits used to store the ECC code.
The MCH provides a maximum DRAM address decode space of 4GB. The MCH does not remap
APIC memory space in hardware. It is the BIOS or system designers responsibility to limit DRAM
population so that adequate PCI, AGP, High BIOS, and APIC memory space can be allocated.