Line Interface Modules
LCE-16 LIM Overview
032R440-000
Xedge 6000 Hardware
5-33
Issue 17
Installation & Setup Guide
LCE-16 Connector Pin/Signal Designations
shows the link, pin/signal and input/output designations for the front panel Link 0-7 and
Link 8-15 connectors. All A/B signal pairs listed in the Signal Name column require twisted pair
wiring. Refer to Note 1 and Note 1 at the end of this table for additional information.
Table 5-12
Connector Pin / Signal / Input / Output List, Link 0-7 and Link 8-15
Link
Pin
Signal Name
Input/
Output
Link
Pin
Signal Name
Input/
Output
0/8
1
Chassis Ground
n/a
0/8
51
Receive Data-A (RD-A)
Output
0/8
2
Carrier Detect-A (DCD-A)
(see Note 2)
0/8
52
Receive Data-B (RD-B)
Output
0/8
3
Transmit Data-A (TD-A)
Input
0/8
53
Receive Timing-A (RT-A)
Output
0/8
4
Transmit Data-B (TD-B)
Input
0/8
54
Receive Timing-B (RT-B)
Output
0/8
5
Transmit Timing-A (TT-A)
(see Note 1)
0/8
55
External Timing-A (ET-A)
Input
0/8
6
Transmit Timing-B (TT-B)
(see Note 1)
0/8
56
External Timing-B (ET-B)
Input
0/8
7
Clear to Send-A (CTS-A)
Output
0/8
57
Request to Send-A (RTS-A)
Input
0/8
8
Clear to Send-B (CTS-B)
Output
0/8
58
Request to Send-B (RTS-B)
Input
0/8
9
DCE Ready-A (DSR-A)
Output
0/8
59
DTE Ready-A (DTR-A)
Input
0/8
10
DCE Ready-B (DSR-B)
Output
0/8
60
DTE Ready-B (DTR-B)
Input
1/9
11
Chassis Ground
n/a
0/8
61
Signal Common
n/a
0/8
12
Carrier Detect-B (DCD-B)
(see Note 2
1/9
62
Signal Common
n/a
1/9
13
Receive Data-A (RD-A)
Output
1/9
63
Transmit Data-A (TD-A)
Input
1/9
14
Receive Data-B (RD-B)
Output
1/9
64
Transmit Data-B (TD-B)
Input
1/9
15
Receive Timing-A (RT-A)
Output
1/9
65
Transmit Timing-A (TT-A)
(see Note 1)
1/9
16
Receive Timing-B (RT-B)
Output
1/9
66
Transmit Timing-B (TT-B)
(see Note 1)
1/9
17
External Timing-A (ET-A)
Input
1/9
67
Clear to Send-A (CTS-A)
Output
1/9
18
External Timing-B (ET-B)
Input
1/9
68
Clear to Send-B (CTS-B)
Output
1/9
19
Request to Send-A (RTS-A)
Input
1/9
69
DCE Ready-A (DSR-A)
Output
1/9
20
Request to Send-B (RTS-B)
Input
1/9
70
DCE Ready-B (DSR-B)
Output
1/9
21
DTE Ready-A (DTR-A)
Input
2/10
71
Chassis Ground
n/a
1/9
22
DTE Ready-B (DTR-B)
Input
3/11
72
Chassis Ground
n/a
2/10
23
Receive Data-A (RD-A)
Output
2/10
73
Transmit Data-A (TD-A)
Input
2/10
24
Receive Data-B (RD-B)
Output
2/10
74
Transmit Data-B (TD-B)
Input
2/10
25
Receive Timing-A (RT-A)
Output
2/10
75
Transmit Timing-A (TT-A)
(see Note 1)
2/10
26
Receive Timing-B (RT-B)
Output
2/10
76
Transmit Timing-B (TT-B)
(see Note 1)
2/10
27
External Timing-A (ET-A)
Input
4/12
77
Chassis Ground
n/a
2/10
28
External Timing-B (ET-B)
Input
5/13
78
Chassis Ground
n/a
3/11
29
Receive Data-A (RD-A)
Output
3/11
79
Transmit Data-A (TD-A)
Input
3/11
30
Receive Data-B (RD-B)
Output
3/11
80
Transmit Data-B (TD-B)
Input
3/11
31
Receive Timing-A (RT-A)
Output
3/11
81
Transmit Timing-A (TT-A)
(see Note 1)
3/11
32
Receive Timing-B (RT-B)
Output
3/11
82
Transmit Timing-B (TT-B)
(see Note 1)
3/11
33
External Timing-A (ET-A)
Input
6/14
83
Chassis Ground
n/a
3/11
34
External Timing-B (ET-B)
Input
7/15
84
Chassis Ground
n/a
4/12
35
Receive Data-A (RD-A)
Output
4/12
85
Transmit Data-A (TD-A)
Input
