
Cinterion
®
LTE Terminals Hardware Interface Description
3.3 Terminal Circuit
47
ELSxT_HID_v04
2018-09-04
Confidential / Preliminary
Page 26 of 102
3.3
Terminal Circuit
shows a general LTE Terminal block diagram that includes all variants.
Figure 6:
LTE Terminals circuit block diagram
D
-S
ub 9-
pi
n
Level -
shifter
RS
23
2 in
te
rf
ac
e
EMC
R
S
2
32
dr
iv
er
Vreg
SI
M
ca
rd
ho
ld
e
r
SI
M ca
rd
in
te
rf
ac
e
CCxxx
EM
C
Batt+
LED
green
LED
orange
LED drivers
LED
V180
SM
A
f
em
a
le
A
nt
enn
a i
n
te
rf
ac
e
RFout
W
es
ter
n J
a
ck
6-
pi
n
Po
w
er
s
u
pp
ly
EMC
(RST)
EMC
power
DC/DC
converter
Vreg
Line
regulator
ON
EMERG_RST
Batt+
Batt+
(Hardware )
Watchdog
E
the
rn
et
RJ
45
LED
link/
active
Fi
lte
r
10/100 Ethernet
sub-system
US
B
GP
IO
co
nn
ec
to
r
12
-p
in
EMC
Driver
bidirect.
GPIO
USB
Electronic
SIM
(opt.)
E
th
er
n
et
c
onn
ec
to
r
SM
A
fe
m
a
le
SM
A
fe
m
a
le
RFin
Rfin
A
nte
nn
a i
n
te
rf
ac
es
(M
ai
n an
te
nn
a,
R
x
di
ve
rs
ity
)
GP
IO
co
nn
ec
to
r
8-
pi
n
EM
C
Driver
Java
module
Supply
VCCref
I²C
WD_RETRIG
(GPIO8)
PoE
1000
10/
100