GE H
EALTHCARE
RAFT
V
OLUSON
E8 / V
OLUSON
E6
D
IRECTION
KTD102576, R
EVISION
7
DRAFT (A
UGUST
23, 2012)
S
ERVICE
M
ANUAL
5-24
Section 5-3 - FrontEnd Processor
Section 5-3
FrontEnd Processor
Voluson E8 / Voluson E6 Front End components described in the sub-sections:
Figure 5-5 Front End Processor - Block diagram
B
a
ck
E
n
d
RFI
RF-Interface
RSR
RST
RTM Rx/Tx
Motherboard
RTP Secondary
Power Supply
Probe / Code Select, serial 10 Mb/s
Hall, Probe Code
1
, ...
RTK Mainboard
PCI 32 Bit
33 MHz,
132 MB/s
RTN Primary
Power Supply
RTF
ProbeConnect
FPGA
RSR
RSR
RST
RST
BF Rx Data, LVDS, 14 pairs
50MHz Clock
Rx coeff. LVDS, 8 pairs
600Mb/s
BF Config (CW Gain, Test, ...)
Serial 10 Mb/s
Tx coeff. LVDS, 8 pairs,
600 Mb/s
FPGA Config. Serial 50MHz
I²
C
B
u
s
Ser
ial
I/
F to
Motor
Power Dri
vve
CPP Analog
I/O
FrontEnd
DSP Motor control
(Digital Signal Processor)
Interface
Processing
Mains
Power
Voltage Supply: +3,3V, -3,3V, 2,0V, TxPower 1, TxPower 2
FPGA