Embedded PC/RTOS Features 41
3.6 VME Control
shows
the
register
definitions
for
the
VMIVME
‐
7807/VME
‐
7807RC
(offset
from
BAR0).
Please
refer
to
for
more
information
concerning
BAR0.
Table 3-13 Register Definitions Offset from BAR0
Register and Offset
Bit Name
Bit
Definition
VMECOMM
Offset 0x00
MEC_SEL
0
Master Big-Endian Enable bit
1=Big Endian, 0=Little Endian
SEC_SEL
1
Slave Big-Endian Enable bit
1=Big Endian, 0=Little Endian
ABLE
2
Auxiliary BERR Logic Enable bit
1=Aux. BERR Enabled, 0=Aux. BERR Disabled
BTO
3
Bus Error Timer Enabled
1=Enable, 0=Disabled
BTOV [1:0]
5:4
Timeout Value
00 - 16
μ
s
01 - 64
μ
s
10 - 256
μ
s
11 - 1.00 ms
BERRI
6
BERR Interrupt Enable
1=Interrupt Enabled, 0=Interrupt Disabled
BERRST
7
BERR Status Read/Clear bit
1=Clear BERR status, 0=Do nothing
SFENA
8
Enables generation of VME SYSFAIL upon WDT
timeout
1=Enable SYSFAIL generation, 0=Disable
Unused
9
Not Used
BPENA
10
Endian Conversion Bypass bit
1=bypass, 0=Not bypassed
VBENA
11
VME Enable bit (VBENA)
1=Enabled, 0=Disabled
Unused
31:12
Not Used
VBAM
0x04
VME_ADDR
5:0
Latched VME Address Modifier
Unused
31:6
Not Used
SEC_SEL
0x001
VBAR
0x08
VME_ADDR
All
Latched VME Address