GE MAC 5000, Руководство по обслуживанию на месте

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Revision B 5-10
CPU Theory of Operation: Theory of Operation
MAC 5000 resting ECG analysis system
2000657-002
its bit sampling circuit. It is possible for the ECG data to be all zeros or
ones, so runs of as many as 80 zeros or ones could occur before a marker
word is encountered in the data stream (which contains at least one "1"
and one "0" to break any runs in the data).
The acquisition module supports a special "code update" mode for
rapid reprogramming of it’s on-board code memory. To increase the
update speed, the acquisition module echoes each uploaded code byte
with a single reply word rather than the usual 16 word data packet. The
FPGA receive logic provides a special 1 word reception mode to
accommodate this.
Thermal Printhead Interface The StrongARM sends print data to the thermal print head through a
buffered serial interface. The FPGA implements the data buffer,
serializer, strobe/latch pulse generator and power switch gate drive
pump. Special interlocks are implemented to prevent stuck strobe
signals or printing when the battery voltage is critically low.
Each print line requires 1728 bits of data. To conserve FPGA resources,
each line is divided into three chunks of 512 bits each, with one leftover
chunk of 192 bits. The FPGA provides a single 16 word x 32 bit buffer
(512 bits) to hold the print line data. After writing a chunk of data to the
buffer, the StrongARM enables serialization of the data by reading one
of two registers (to support the serialization of either a full 512 bit or
partial 192 bit buffer). When the entire print line has been loaded, the
StrongARM cues a print strobe by writing the required strobe width
value to the strobe/latch pulse generator.
When the strobe register contains a non-zero value, the power switch
gate pump produces a differential clock signal to drive an external diode
voltage doubler. The output of the voltage doubler drives the gate of a
power MOSFET which provides power to the print head.
A special test mode is provided to allow testing of the thermal print
head. In test mode, print head power is disabled and the strobe signal is
driven continuously. This allows individual print dots to be driven with
a small test current. The resulting voltage drop may be measured to
either determine the dot’s resistance or a least determine of the dot is
open.
Serial EEPROM Interface A standard SPI interface is provided for connection to a serial EEPROM
memory. The StrongARM exchanges a byte of data with the EEPROM by
writing a value to the interface register. Data is clocked at 4MHz, quickly
enough that no interrupt support is required. The StrongARM polls a
ready bit to determine when the transfer is complete.
BBus Interface There are several I/O functions poorly suited to direct control by the
StrongARM, whether for reasons of software complexity or power
consumption. These I/O functions are provided by three 68HC705
microcontrollers placed strategically around the board (Moe, Larry and
Shemp). Each of these three microcontrollers must communicate with
the StrongARM. BBus is a simple 1-wire point-to-point interface
designed specifically for this purpose. The FPGA provides a single BBus