342-86400-445PS
Issue
4.0
October
2006
Page
56
Copyright
GE Multilin Inc. 2002
Transmit Signaling
Each ProSLIC device continuously monitors its respective line and detects on-
hook, off-hook, or ring-ground (for GS application) states. The microcontroller
reads ProSLIC registers and encodes the line states into A and B signaling bits
to be passed to the FPGA.
The FPGA maps the signaling bits into the VT overhead bytes in the position
determined by the DS0 channel numbers set.
The Transmit Signaling condition can be monitored through the VistaNET
software.
Receive Signaling
The receive signaling bits are extracted from the received JVT bus stream by the
FPGA and then passed to the microcontroller.
The microcontroller interprets the received signaling bits in conjunction with the
transmit signaling bits (line on-hook or off-hook) and issues the command to the
respective ProSLIC device to output or not to output ringing voltage to its line. In
GS application, the ProSLIC device also sets Tip to ground when instructed.
The Receive Signaling condition can be monitored through the VistaNET
software.
Microprocessor Operation
U4, a 68HC16Z1 microprocessor, is the CPU for the 86445-32 2W FXS unit. For
memory the micro uses a 128 kbytes RAM (U6), a 128 kbytes Flash EEROM
(U7) and a 1-kbyte internal high speed RAM. The CPU provides the following:
•
Communication with the user through the Craft Interface port
•
Control of all front panel LEDs and monitoring of the ACK push-button
•
Monitoring of the unit temperature sensor (U5) and reporting unit
temperature
•
Unit initialization and configuration of the FPGA (U10)
