eRide
OPUS 6/
eRide
OPUS 7 GV-86/ GV-87
Dead Reckoning User
’
s Guide
SE16-900-002-00
7
FURUNO ELECTRIC CO., LTD. All rights reserved.
4.4 ITG-3500 and AIS328DQ
I/O signal
Description
Interface connection destination
eRideOPUS 6/7
GV-86/ 87
RESET
External reset signal
NRST
RST_N
SCL
I2C clock
TXD2_SCL
TXD2_SCL
SDA
I2C address/data bus
RXD2_SDA
RXD2_SDA
Figure 4.4 Reference Circuit of ITG-3500 and AIS328DQ
U7
AIS328DQ
NC
1
NC
2
INT_2
3
Reserv ed
4
VDD
5
GND
6
IN
T
_1
7
GN
D
8
GN
D
9
GN
D
10
SP
C
/SC
L
11
CS
12
Reserv ed
13
VDD_IO
14
SDO/SA0
15
SDI/SDO/SDA
16
NC
17
NC
18
NC
19
NC
20
NC
21
NC
22
NC
23
NC
24
VCC
C5
10uF
C4
0.1uF
U1
XC8101AA01-GR-G
VOUT
1
VSS
2
CE
3
VIN
4
C2
0.1uF
U2
ITG-3500
SDA/SDI
1
NC
2
VDDIO
3
/CS
4
R
ES
V
5
AD
0/
SD
0
6
R
EG
OU
T
7
F
SY
N
C
8
VDD
9
INT
10
NC
11
GND
12
NC
13
R
ES
V-G
14
NC
15
SC
L/
SC
LK
16
C3
0.1uF
C1
0.01uF
VCC
R2
10k
R1
10k
VCC
VCC
RESET
SDA
SCL
(*4)
(*3)
(*3)
(*1)
(*1)
(*1)
(*2)
(*2)
(*2)