Fujitsu MB95630H Series, Руководство по оборудованию

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MB95630H Series
MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED 291
CHAPTER 17 CLOCK SUPERVISOR COUNTER
17.2 Configuration
17.2 Configuration
The clock supervisor counter consists of the following blocks:
• Control circuit
• Clock Monitoring Control Register (CMCR)
• Clock Monitoring Data Register (CMDR)
• Time-base timer output selector
• Counter source clock selector
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Block Diagram of Clock Supervisor Counter
Figure 17.2-1 is the block diagram of the clock supervisor counter.
Figure 17.2-1 Block Diagram of Clock Supervisor Counter
Time- bas e timer o u tp u t
M a in o s cill a tion clock
Sub -o s cill a tion clock
Edge detection
8 - b it Co u nter
1 s t:
2nd:
co u nting s t a rt s
co u nting s top s
Control Circ u it
Clock Monitoring Control Regi s ter (CMCR) Clock Monitoring D a t a Regi s ter (CMDR)
CLK
Co u nter en ab led
Intern a l B us
3
Time- bas e
Timer
O
u tp u t
S elector
Co u nter
S o u rce
Clock
S elector