Fujitsu MB90460 Series, Руководство по оборудованию, Страница: 99 / 739

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CHAPTER 5 CLOCK
5.2 Block Diagram of the Clock Generation Block
The clock generation block consists of five blocks:
• System clock generation circuit
• PLL multiplier circuit
• Clock selector
• Clock selection register (CKSCR)
• Oscillation stabilization wait interval selector
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Block Diagram of the Clock Generation Block
Figure 5.2-1 shows a block diagram of the clock generation block.
Figure 5.2-1 also includes the standby control circuit and time-base timer circuit.
Figure 5.2-1 Block Diagram of the Clock Generation Block
X0
2
X1
R S TX
R S T
S TP R S T S LP CG1 CG0 RE S V S PL TMD
RE S V W S 0 MCM MC S C S 1 C S 0 W S 1 RE S V
3
2
Low power mode control regi s ter (LPMCR)
Pin
Pin
Pin
Divide-
b y-2
Divide-
b y-512
Divide-
b y-2
Divide-
b y-4
Divide-
b y-4
PLL m u ltipiler
circ u it
S y s tem clock
gener a tion circ u it
Time- bas e timer
S top s ign a l
Rele as e re s et
C a ncel interr u pt
CPU clock
Pin Hi-z control
Clock s elector
Clock s election regi s ter (CK S CR)
S top a nd s leep s ign a l s
M a chine clock
M a in clock
O s cill a tion s t ab iliz a tion
w a it interv a l s elector
O s cill a tion s t ab iliz-
- a tion w a it i s p ass ed
CPU clock
control circ
u it
Pin high
imped
a nce
control circ u it
Intern a l re s et
gener a tion
circ u it
Intern a l re s et
Peripher a l clock
control circ u it
CPU intermittent
oper
a tion s electer
S elect intermittent cycle s
S t a nd b y control
circ u it
Peripher a l clock
Clock gener a tor
x1 x2 x 3 x4
Divide-
b y-4