Fujitsu MB90390 Series, Руководство по оборудованию

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CHAPTER 5 CLOCKS
5.2 Block Diagram of the Clock Generation Block
The clock generation block consists of five blocks:
• System clock generation circuit
• PLL multiplier circuit
• Clock selector
• Clock selection register (CKSCR)
• Oscillation stabilization wait time selector
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Block Diagram of the Clock Generation Block
Figure 5.2-1 shows a block diagram of the clock generation block.
Figure 5.2-1 Block Diagram of the Clock Generation Block
Pin
Pin
X0
X1
Divide-
b y-2
S y s tem clock
gener a tion circ u it
Divide-
b y-1024
Divide-
b y-2
Divide-
b y-4
Divide-
b y-4
Divide-
b y-4
Divide-
b y-2
Time- bas e Timer
W a tchdog Timer
HCLK
M a inclock
Note: The Clock Mod u l a tor i s not s hown in thi s di a gr a m, ple as e refer to
ch a pter 6 for det a il s .
S TP S LP S PL R S T TMD CG1 CG0
Low-Power Con su mption Mode Control Regi s ter (LPMCR)
PLL m u ltiplier circ u it
O s cill a tion
w a it time
Clock
-
MCM W S 1 W S 0
-
MC S C S 1 C S 0
Clock S election regi s ter (CK S CR)
2
S elector
2
interv a l s elector
s t ab iliz a tion
Pin high-
imped a nce
control circ u it
Intern a l re s et
gener a tion
circ u it
CPU clock
control
circ u it
Peripher a l
clock control
circ
u it
S t a nd b y
control
circ u it
CPU intermittent
oper a tion
s elector
Pin
R S T
Interr u pt
cle a ring
O s cill a tion s t ab iliz a tion w a it cle a r
M a chine clock
S top s ign a l
S top a nd
s leep s ign a l s
Interm.
cycle
s el.
Pin high-
imped
a nce
control
Intern a l
re s et
CPU
clock
-
C S 2
Bit 8 of PLL a nd
S peci a l Config u r a tion
Control Regi s ter
(P S CCR) : b it 8
Peripher a l
clock