
AN07-00200-03E
90
Table 5-1 Description of the entire LIN communication control registers and setting values
Register name
Set value (contents)
Explanation
SCR_PEN
0 (no parity)
Parity authorization bit
SCR_P
0 (even parity)
Parity selection bit
SCR_SBL
0 (1 bit)
Stop bit length selection bit
SCR_CL
1 (8 bit)
Data length selection bit
SCR_AD
0 (data frame)
Address / data format selection bit
SCR_CRE
1 (clear flag)
Clear reception error flag bit
SCR_RXE
0 (Receive prohibited)
Receive prohibition enable bit
SCR_TXE
1 (Transmit enabled)
Transmit enable bit
SMR_MD1
1 (mode 3)
Operation mode selection bit
SMR_MD0
1 (asynchronous LIN mode)
SMR_OTO
0 (use external clock)
1-to-1 external input enable bit
SMR_EXT
0 (use baud rate generator)
External serial clock source selection bit
SMR_REST
0
Reload counter restart bit
SMR_UPCL
1 (LIN-UART reset)
Programmable clear bit
(LIN-UART software reset)
SMR_SCKE
0 (general I/O port or LIN-UART clock input
pin)
Serial clock output enable bit
SMR_SOE
1 (LIN-UART serial data output pin)
Serial data output enable bit
SSR_BDS
0 (LSB first (transfer from least significant
bit))
Transfer direction selection bit
SSR_RIE
1 (Receive interrupt enable)
Receive interrupt request enable
SSR_TIE
0 (Transmit interrupt prohibited)
Transmit interrupt request enable
ESCR_LBIE
0 (LIN synch break detection interrupt
prohibited)
LIN synch break detection interrupt enable
bit
ESCR_LBD
0 (LIN synch break detection flag clear)
LIN synch break detection flag bit
ESCR_LBL1
0
LIN synch break length selection bit
ESCR_LBL0
0 (13 bits)
ESCR_SOPE
0 (serial output pin access prohibited)
Serial output pin direct access enable bit
ESCR_SIOP
0
Serial I/O pin direct access enable bit
ESCR_CC0
0
Continuous clock output enable bit
ESCR_SCES
0
Sampling clock edge selection bit