55
55
55
55
6:SWAP
- When this switch is OFF, the external FLASH memory is mapped to
the UMB and the SRAM is mapped the LMB. If the switch is ON, these
memory areas are swapped.
7:UART0/1
- In the Async Serial Programming mode if the switch is ON, the
serial communication goes to the UART1 port of the CPU. If the switch is OFF,
it goes to the UART0. Note, that serial cable is still connected to the User UART
interface connector, so that the user doesn’t have to change its position.
8:USW
- The state of this switch (OR-ed with the state of UKEY), can be read
in the SCDS register (address C0
H
). Both Fujitsu debug monitor and PE debug
kernel use this switch to find out whether to run the user program or not after
reset.
When this switch is ON after the reset, the kernel runs the user program (if there
is any). When it is OFF, the kernel waits for communication with PC.
After the user program is run, the user can use the USW switch (and/or User
Key button) as one of his program’s input.
Note: for compatibility reasons, the User key state and the User switch state
are logically OR-ed to form the value of the USW bit in the SCDS register
(address C0
H
). Therefore during the reset, holding the User key will have the
same effect as switching the USW to ON (though, this OR-ing will not be
supported in the future, so the USW and UKEY will be totally independent).
The state of the User Key can be still independently read from the Hardware
Status Register (address C0
H
).
Factory default setting:
See the figure above: the setting 2 (UMD1) = ON, 3 (UMD2)=ON,
4(FLASH8/16)=ON means that the CPU will start in the ‘External vector mode
1’ and the external FLASH memory interface is configured to 16 bits mode. The
memory model is standard, with external FLASH in the UMB and SRAM in
LMB.
Reset button:
This button resets the whole system – CPU and FPGA, so it should be used as a
“hard” reset. To reset the CPU only, please use the reset button on the CPU
board.
J U M P E R S
J9
:
User UART RTS-CTS loopback
In the
1-2 position
, this jumper makes the RTS-CTS loopback on the FPGA
RS232 interface.
In the
2-3 position
, it connects the RTS signal to the User UART and thus
allows the hardware flow control to work properly.
UART
jumpers:
