Freescale Semiconductor MPC5748G EVB, Руководство пользователя, Страница: 31 / 88

Default Jumper Summary Table
MPC5748G EVB User Guide, User Guide, Rev. 0, 08/2015
Freescale Semiconductor, Inc. 31
10. Default Jumper Summary Table
The following tables detail the default (D) jumper configuration of the EVB and daughtercards
Table 26. Default Jumper Positions (Main Board)
Jumper Default
Posn
PCB
Legend
Description
J1 Posn 1-2 Fitted ( D ) BGE FlexRay B PHY Bus Guardian Enable (Transmitter is enabled )
J1 Posn 3-4 Fitted ( D ) EN FlexRay B PHY is enabled
J1 Posn 5-6 Fitted ( D ) STBN FlexRay B PHY will not enter Standby Mode
J1 Posn 7-8 Fitted ( D ) WAKE FlexRay B PHY Wakeup signal pulled low
J2 Posn 1-2 Fitted ( D ) BGE FlexRay A PHY Bus Guardian Enable (Transmitter is enabled )
J2 Posn 3-4
Fitted ( D ) EN FlexRay A PHY is enabled
J2 Posn 5-6 Fitted ( D ) STBN FlexRay A PHY will not enter Standby Mode
J2 Posn 7-8 Fitted ( D ) WAKE FlexRay A PHY Wakeup signal pulled low
J3 Posn 1-2 Fitted ( D ) TX MCU PC5 is connected to FlexRay A transceiver TX
J3 Posn 3-4 Fitted ( D ) TXEN MCU PE2 is connected to FlexRay A transceiver TXEN
J3 Posn 5-6
Fitted ( D ) RX MCU PE3 is connected to FlexRay A transceiver RX
J4 Posn 1-2
Fitted ( D ) TX MCU PE4 is connected to FlexRay B transceiver TX
J4 Posn 3-4 Fitted ( D ) TXEN MCU PC4 is connected to FlexRay B transceiver TXEN
J4 Posn 5-6 Fitted ( D ) RX MCU PE5 is connected to FlexRay B transceiver RX
J5 1-2 (D) MII Ethernet PHY is configured in MII mode
J6 (X1) 1-2 (D) Ethernet PHY X2 clock is connected to 25MHz xtal
J7 (X2) 1-2 (D) Ethernet PHY X1 clock is connected to 25MHz xtal
J8 (RST) 1-2 (D) NORM The Ethernet PHY will be reset along with MCU reset
J9 (EN) Fitted ( D ) Reset from reset switch and debug connectors is active
J10 (LIN0) 1-2 Fitted ( D ) RX MCU LIN0_RX signal (PB3) is routed to LIN0 interface
J10 (LIN0) 3-4 Fitted ( D ) TX MCU LIN0_TX signal (PB2) is routed to LIN0 interface
J11 (Master_EN) Fitted ( D ) LIN0 is configured in Master Mode
J12 (LIN1) 1-2 Fitted ( D ) RX MCU LIN1_TX signal (PC7) is routed to LIN1 interface
J12 (LIN1) 3-4
Fitted ( D ) TX MCU LIN1_RX signal (PC6) is routed to LIN interface
J13 (Master_EN)
Fitted ( D ) LIN1 is configured in Master Mode
J14 (CAN1) 1-2
Fitted ( D ) TX MCU CAN1_TX signal (PC10) is routed to CAN interface
J14 (CAN1) 3-4 Fitted ( D ) RX MCU CAN1_RX signal (PC11) is routed to CAN interface
J15 (CAN0) 1-2 Fitted ( D ) TX MCU CAN0_TX signal (PB0) is routed to CAN interface
J15 (CAN0) 3-4 Fitted ( D ) RX MCU CAN0_RX signal (PB1) is routed to CAN interface
J16 Posn 1-2 Fitted ( D ) RX MCU LIN2_RX signal (PC9) is routed to the FTDI interface
J16 Posn 3-4 Fitted ( D ) TX MCU LIN2_TX signal (PC8) is routed to the FTDI interface
J17 Fitted ( D ) Output from RV1 is routed to MCU PB4 pin
J18 (1V25L) Fitted ( D ) 1.25V Linear regulator output is routed to daughter card
J19 (5V0S) Fitted ( D ) 5.0V Switching regulator output is routed to daughter card
J20 (3V3L) Fitted ( D ) 3.3V Linear regulator output is routed to daughter card
J21 (5V0L) Fitted ( D ) 5.0V Linear regulator output is routed to daughter card
J22 (3V3S) Fitted ( D ) 3.3V Switching regulator output is routed to daughter card
J23 (INPUT SEL) 1-2 (D) 12V 1.25V Linear regulator is powered from main 12V
J24 (HVA) 1-2 (D) 3V3 EVB peripherals in HVA domain are set to use I/O voltage of 3.3V
J25 (HVB) 1-2 (D) 3V3 EVB peripherals in HVB domain are set to use I/O voltage of 3.3V
J26 (3V3) Fitted ( D ) The hex encoder switch is powered with 3.3V (functional)