Freescale Semiconductor MPC5632M, Руководство пользователя

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MPC563XM Reference Manual, Rev. 1
Freescale Semiconductor 925
Preliminary—Subject to Change Without Notice
• If SCM is implemented as RAM, load the eTPU application code (see Section 23.4.2.6, “SCM
access ).
• Initialize the SCM MISC logic (see Section 23.4.10.3.1, “SCM Test - Multiple Input Signature
Calculator ).
• Initialize the eTPU time base configuration registers (ETPUTBCR) to setup:
— TCR1 and TCR2 prescalers and clock sources.
— Select digital filtering mode.
— TCRCLK signal filter control.
— Angle mode operation (if necessary).
• Initialize the eTPU engine configuration register (ETPUECR) to setup:
— Entry table base.
— Filter prescaler clock control.
• Initialize eTPU Red Line configuration registers (ETPUREDCR) to setup TCR1/2 resource
Client/Server operation.
• Write to the Channel Configuration registers (ETPUCxCR) to choose the Function to be performed
by each channel, and its parameter base address.
• Write to channel status control register (ETPUCxSCR) to choose the possible variations within the
function flow (FM bits).
• Write to SPRAM for parameter initialization of each configured channel.
• Write to channel x Host Service Request registers (ETPUCxHSRR) to initialize the active
channels.
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• Write to the channel interrupt enable register (ETPUCIER) if interrupts are to be enabled from the
appropriate channels. Likewise for Data Transfer Requests (ETPUCDTRER). This can be done
through ETPUCxCR.
• Write to channel x configuration registers (ETPUCxCR) to enable each channel by assigning it a
high, middle, or low priority (CPR field).
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• Monitor the Host service request registers (ETPUCxHSRR) for completion of initialization.
• Write ETPUMCR bit GTBE=1 to start TCR1/TCR2 time base counting at same time in both
Engines (may be done before or never, depending on the particular application and use of Red Line
bus).
See Section 23.6.2, “Initialization Code Example .
23.5.2 Reset Options
23.5.2.1 Hardware Reset
Hardware reset is achieved by assertion of SoC synchronous reset. Both Engines and common logic is
reset, and even the System Configuration and Global Channel registers assume their reset values.
1. This operation is done before enabling active channels to avoid time events happening before the channel initialization.