SPIx_PUSHR field descriptions (continued)
Field
Description
30–28
CTAS
Clock and Transfer Attributes Select
Selects which CTAR to use in master mode to specify the transfer attributes for the associated SPI frame.
In SPI Slave mode, CTAR0 is used. See the chip configuration details to determine how many CTARs this
device has. You should not program a value in this field for a register that is not present.
000
CTAR0
001
CTAR1
010
Reserved
011
Reserved
100
Reserved
101
Reserved
110
Reserved
111
Reserved
27
EOQ
End Of Queue
Host software uses this bit to signal to the module that the current SPI transfer is the last in a queue. At
the end of the transfer, the EOQF bit in the SR is set.
0
The SPI data is not the last data to transfer.
1
The SPI data is the last data to transfer.
26
CTCNT
Clear Transfer Counter
Clears the TCNT field in the TCR register. The TCNT field is cleared before the module starts transmitting
the current SPI frame.
0
Do not clear the TCR[TCNT] field.
1
Clear the TCR[TCNT] field.
25–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23–22
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
21–16
PCS
Select which PCS signals are to be asserted for the transfer. Refer to the chip configuration details for the
number of PCS signals used in this MCU.
0
Negate the PCS[x] signal.
1
Assert the PCS[x] signal.
15–0
TXDATA
Transmit Data
Holds SPI data to be transferred according to the associated SPI command.
44.3.8 PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE)
Specifies data to be transferred to the TX FIFO. An 8- or 16-bit write access to PUSHR
transfers all 32 bits to the TX FIFO.
Memory Map/Register Definition
K22F Sub-Family Reference Manual , Rev. 3, 7/2014
1066
Freescale Semiconductor, Inc.
Содержание MK22FN256VDC12
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