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Slide 58
Lab 3 – Internal Clock Source
ICS Control Register 2
BDIV bits select the amount to divide down the clock source selected by the CLKS bits
RANGE selects high frequency (1) or low frequency (0) range for the external oscillator
HGO configures the external oscillator for high gain (1) or low power (0) operation
LP controls whether the FLL is disabled (1) or not (0) in FLL bypassed modes
EREFS selects whether an oscillator (1) or an external clock source (0) is used for the
external reference clock
ERCLKEN enables (1) or disables (0) the external reference clock for use as ICSERCLK
EREFSTEN controls whether the external reference clock remains enabled (1) or not (0)
when the ICS enter stop mode
