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APPENDIX A
PALLV16V8 code – PALASM4
TITLE
U10_BUS_ARBITRATION_&_GPIO
PATTERN
P00001
REVISION
1
DATE
19th January 1999
AUTHOR
Pete Highton
COMPANY
Motorola SPS (c) 1999
CHIP U10
PALCE16V8
PIN 1
CLK
COMBINATORIAL
PIN 2
/BR
COMBINATORIAL
PIN 3
/BR_HW
COMBINATORIAL
PIN 4
/BD
COMBINATORIAL
PIN 5
/CS3
COMBINATORIAL
PIN 6
U15OP
COMBINATORIAL
PIN 7
NC
COMBINATORIAL
PIN 8
NC
COMBINATORIAL
PIN 9
/WR
COMBINATORIAL
PIN 10
GND
PIN 11
NC
PIN 12
/BG_HW
COMBINATORIAL
; O/P
PIN 13
/BG
COMBINATORIAL
; O/P
PIN 14
/IORD
COMBINATORIAL
; O/P
PIN 15
/IOWR
COMBINATORIAL
; O/P
PIN 16
/U15_OE
COMBINATORIAL
; O/P
PIN 17
NC
COMBINATORIAL
PIN 18
NC
COMBINATORIAL
PIN 19
/RD
COMBINATORIAL
; O/P
PIN 20
VCC
EQUATIONS
RD = /WR
IORD = CS3*/WR
; GPIO Read enable
IOWR = CS3*WR
; GPIO write enable
U15_OE = U15OP + IORD
; If device is O/P, permanent OE when read
; Bus arbitration...
BG = (BD + (BR * /BR_HW))
; External hardware has priority
BG_HW = BR_HW * /BG
; Bus grant to the target H/W
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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