Freescale Semiconductor MC9S08PT60, Справочное руководство

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ICS_C1 field descriptions (continued)
Field Description
1. Reset default
2
IREFS
Internal Reference Select
The IREFS bit selects the reference clock source for the FLL.
0 External reference clock selected.
1 Internal reference clock selected.
1
IRCLKEN
Internal Reference Clock Enable
The IRCLKEN bit enables the internal reference clock for use as ICSIRCLK.
0 ICSIRCLK inactive.
1 ICSIRCLK active.
0
IREFSTEN
Internal Reference Stop Enable
The IREFSTEN bit controls whether or not the internal reference clock remains enabled when the ICS
enters stop mode.
0 Internal reference clock is disabled in stop.
1 Internal reference clock stays enabled in stop if IRCLKEN is set or if ICS is in FEI, FBI, or FBILP mode
before entering stop.
1. Reset default
8.6.2 ICS Control Register 2 (ICS_C2)
Address: 3038h base + 1h offset = 3039h
Bit 7 6 5 4 3 2 1 0
Read
BDIV LP
0
Write
Reset 0 0 1 0 0 0 0 0
ICS_C2 field descriptions
Field Description
7–5
BDIV
Bus Frequency Divider
Selects the amount to divide down the clock source selected by the CLKS bits. This controls the bus
frequency.
000 Encoding 0 - Divides selected clock by 1.
001 Encoding 1 - Divides selected clock by 2.
010 Encoding 2 - Divides selected clock by 4.
011 Encoding 3 - Divides selected clock by 8.
100 Encoding 4 - Divides selected clock by 16.
101 Encoding 5 - Divides selected clock by 32.
110 Encoding 6 - Divides selected clock by 64.
111 Encoding 7 - Divides selected clock by 128.
Table continues on the next page...
ICS control registers
MC9S08PT60 Reference Manual, Rev. 4, 08/2014
218 Freescale Semiconductor, Inc.