
Support Information
M9328MX21ADSE User’s Manual, Rev. A
3-6
Freescale Semiconductor
96
B_A3
BUFFERED ADDRESS 3 — Buffered address output
97
B_D7
BUFFERED DATA 7— Buffered bidirectional data bus bit
98
B_D15
BUFFERED DATA 15 — Buffered bidirectional data bus bit
99
B_D6
BUFFERED DATA 6 — Buffered bidirectional data bus bit
100
B_D14
BUFFERED DATA 14 — Buffered bidirectional data bus bit
101
B_D5
BUFFERED DATA 5— Buffered bidirectional data bus bit
102
B_D13
BUFFERED DATA 13 — Buffered bidirectional data bus bit
103
B_D4
BUFFERED DATA 4 — Buffered bidirectional data bus bit
104
B_D12
BUFFERED DATA 12 — Buffered bidirectional data bus bit
105
B_D3
BUFFERED DATA 3 — Buffered bidirectional data bus bit
106
B_D11
BUFFERED DATA 11 — Buffered bidirectional data bus bit
107
B_D2
BUFFERED DATA 2 — Buffered bidirectional data bus bit
108
B_D10
BUFFERED DATA 10— Buffered bidirectional data bus bit
109
B_D1
BUFFERED DATA 1 — Buffered bidirectional data bus bit
110
B_D9
BUFFERED DATA 9— Buffered bidirectional data bus bit
111
B_D0
BUFFERED DATA 0— Buffered bidirectional data bus bit
112
B_D8
BUFFERED DATA 8— Buffered bidirectional data bus bit
113
B_A20
BUFFERED ADDRESS 20 — Buffered address output (Reserved)
114
B_A21
BUFFERED ADDRESS 21 — Buffered address output
115
B_A22
BUFFERED ADDRESS 22 — Buffered address output
116
B_A23
BUFFERED ADDRESS 23 — Buffered address output
117
B_A24
BUFFERED ADDRESS 24 — Buffered address output (Reserved)
118
B_A25
BUFFERED ADDRESS 25 — Buffered address output (Reserved)
119
TP25
Test point
Table 3-1. CPU to Base Board PX1/PY1 Connector Signals (continued)
Pin(s)
Signal
Description
Содержание M9328MX21ADSE
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